Pixel Array Structure for Flat Display Panel Gate Driver Integration
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Solution Overview
Problem
The half source driving (HSD) structure for flat display panels reduces the number of data lines, but complicates the operations of the timing controller and increases the manufacturing cost of the gate driver due to the need for complex circuit structures and additional line buffers.
Innovation Solution
A pixel array structure where scan lines are coupled to specific pixels and data lines in a manner that allows the gate driver to be directly disposed on the substrate, reducing the number of data lines and simplifying the control signals, thereby reducing the manufacturing cost of the gate driver and the complexity of the timing controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the half source driving structure is used to reduce the number of data lines, then the fabricating cost of the source driver is reduced, but the operations of the timing controller become complicated and the manufacturing cost of the gate driver increases
Solution Approach 1:
The patent divides the pixel array into multiple regions and assigns different scan line connection patterns to each region. Specifically, it segments the pixel rows into first pixel rows (connected to odd-numbered scan lines) and second pixel rows (connected to even-numbered scan lines), allowing independent control and simplifying the overall driving mechanism
Solution Approach 2:
Instead of following the conventional HSD pattern where scan lines connect to specific pixels in a fixed sequence, the patent inverts the connection logic by enabling any scan line to connect to any pixel row through flexible routing. This inversion allows the timing controller to use simpler, more direct control signals without complex buffering operations
2Quantity of substance
If the half source driving structure is used to reduce the number of data lines, then the fabricating cost of the source driver is reduced, but the manufacturing cost of the gate driver increases due to complicated circuit structure
Solution Approach 1:
The patent makes each scan line serve multiple functions by enabling it to connect to different pixel rows depending on the driving mode. The scan lines are designed with universal connectivity that allows them to function in both conventional HSD mode and the inverted mode, eliminating the need for separate dedicated circuitry for different driving patterns
Solution Approach 2:
The patent introduces dynamic control mechanisms that allow the scan line connections to be reconfigured based on the driving mode. The timing controller can dynamically switch between different connection patterns, making the gate driver circuit adaptable rather than fixed, thereby reducing the need for complex hardwired circuits
3Ease of operation
If additional line buffers are added to the timing controller to support HSD driving, then the control of gate driver and source driver becomes possible, but the overall fabricating price of the gate driver is dramatically increased
Solution Approach 1:
The patent extracts and eliminates the need for additional line buffers from the timing controller by implementing a direct control architecture. Instead of using buffers to temporarily store and manage display data for multiple pixel rows, the system directly controls the gate driver and source driver through simplified control signals, removing the buffering component entirely
Data Source
AI summary
A pixel array structure, a flat display panel and a method for driving a flat display panel thereof are provided. The structure of the pixel array structure and the flat display panel is the structure of the half source driving (HSD). Therefore, by skillfully arranging the coupled relationship between each pixel and each data line, the pixel array structure provided in the present invention can be driven by the gate driver directly disposed on the substrate of the pixel array. Accordingly, not only the fabrication cost of the flat display panel can be reduced, but the manner of the timing controller controlling the gate driver and source driver can also be reduced.