Pixel Array Gate Line Overlap Reduction
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Solution Overview
Problem
The increasing resolution of liquid crystal display panels requires more gate and source drivers, leading to a larger non-display region and higher production costs, as well as wider border lines, which complicates the reduction of costs and minimizes the area of the non-display region.
Innovation Solution
A pixel array design with intersecting scan and gate lines, data lines, and pixel structures on a substrate, where the pixel electrodes are non-overlapping or incompletely overlapping with gate lines, reducing coupling effects and allowing for a more efficient layout that minimizes the mura phenomenon and enhances display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of liquid crystal display panel is enhanced, then the display quality is improved, but the area of non-display region increases and production cost increases
Solution Approach 1:
The patent merges the function of gate drivers into the pixel units themselves. Each pixel unit includes a pixel electrode that can function as both a display element and a gate driver electrode, eliminating the need for separate gate driver circuits in the non-display region. This integration directly reduces the area of the non-display region while maintaining enhanced resolution.
2Measurement precision
If the numbers of gate drivers and source drivers are increased, then the resolution is improved, but the production cost increases
Solution Approach 1:
The patent combines multiple driver functions into the pixel unit structure. The pixel electrode serves dual purposes as both a display element and a gate driver, reducing the total number of separate driver components needed. This integration simplifies the manufacturing process and reduces production costs associated with assembling multiple driver circuits.
Solution Approach 2:
The pixel electrode is designed to perform multiple functions: it serves as the display pixel electrode and simultaneously functions as a gate driver electrode. This multi-functionality reduces the number of separate components needed, thereby lowering production costs while maintaining high resolution.
3Measurement precision
If the numbers of gate drivers and source drivers are increased, then the resolution is improved, but the border line width increases
Solution Approach 1:
By integrating the gate driver function into the pixel unit, the patent eliminates the need for separate gate driver circuits that would occupy space in the border region. This integration allows for narrower border lines while maintaining enhanced resolution.
4Force
If the gate lines and pixel electrodes are completely overlapped, then the coupling effect is strong, but the mura phenomenon occurs
Solution Approach 1:
The patent applies different overlap configurations to different regions. In some pixel units, the pixel electrode partially overlaps with the gate line to maintain necessary coupling, while in other regions, the overlap is reduced or eliminated. This localized variation in overlap quality allows the system to maintain sufficient coupling effect while avoiding the mura phenomenon that occurs with complete overlap.
Data Source
AI summary
A pixel array includes multiple scan lines, multiple gate lines, multiple data lines and multiple pixel structures. The scan lines are disposed on a substrate. The gate lines intersect with the scan lines to demarcate multiple first unit regions and multiple second unit regions. Each gate line electrically connects to one of the scan lines. The data lines intersect with the scan lines and pass through the first unit regions. Each data line is located between two adjacent gate lines. The pixel structures are disposed on the first unit regions. Each pixel structure includes an active device and a pixel electrode. The active device is driven by one corresponding scan line and connects with one corresponding data line. An orthographic projection of each pixel electrode on the substrate is non-overlapped with or incompletely overlapped with an orthographic projection of the corresponding gate lines on the substrate.