Pixel Array Substrate Interlaced Connection Wires
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Solution Overview
Problem
The increasing resolution of display panels necessitates more connection wires, which widens the wire region and deteriorates visual effects due to the inability to reduce the width of this region, affecting the screen ratio and overall display performance.
Innovation Solution
A pixel array substrate design with interlaced signal lines and connection wires, where the connection wires are structured with overlapping segments and insulation layers, allowing for a reduced wire region width and improved visual effects by efficiently arranging the connection wires around a transparent window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display panel is increased, then the display quality is improved, but the number of connection wires increases causing the wire region width to increase and visual effects to deteriorate
Solution Approach 1:
The connection wires are arranged in an interlaced pattern where signal lines and connection wires alternate in position, utilizing spatial arrangement in multiple dimensions to reduce the overall wire region width while accommodating increased wire count for higher resolution displays
Solution Approach 2:
The connection wires are divided into multiple segments with insulation layers between them, allowing for more efficient packing and arrangement of wires in the wire region, thereby reducing the total width required while supporting higher resolution requirements
2Reliability
If more connection wires are arranged around the transparent window, then electrical connectivity is improved, but the wire region width cannot be reduced and visual effects deteriorate
Solution Approach 1:
By arranging connection wires and signal lines in an interlaced alternating pattern, the design utilizes vertical stacking and horizontal alternation to achieve high connectivity with reduced lateral footprint, maintaining electrical reliability while minimizing wire region width
Solution Approach 2:
The signal lines and connection wires are merged into a single interlaced structure rather than being separate parallel regions, allowing shared space utilization and reducing the total wire region width while maintaining all necessary electrical connections
Data Source
AI summary
A pixel array substrate includes a substrate, pixels, and connection wires. The substrate has a transparent window, a wire region, and an active region. The connection wires are disposed in the wire region. Each connection wire is electrically connected to first signal lines of the pixels respectively located on two opposite sides of the transparent window. The connection wires include first and second wire groups. The first wire group includes first connection wires. Each first connection wire has a first segment and a second segment. A first insulation layer is disposed between the first and second segments that are electrically connected to each other. The second wire group includes second connection wires. The first segments of the first connection wires and the second connection wires are overlapped, and the first insulation layer is disposed between the first segments of the first connection wires and the second connection wires.