Pixel Array ADC With Local Clocks for Accurate Column Conversion
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Solution Overview
Problem
Existing analog-to-digital conversion techniques in imaging sensors are limited by the need for rapidly varying signals and synchronized high-speed clocks, which result in conversion errors and power consumption issues, particularly due to clock frequency variations and column-to-column variations in clock skew.
Innovation Solution
The implementation of a local clock system for each analog-to-digital converter, where each converter uses a dedicated or shared clock to count cycles of a ramp signal, with calibration using reference signals to accurately determine the difference between analog signals, allowing for faster and more accurate conversion without the need for synchronized high-speed clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high-speed clock is used for synchronized analog-to-digital conversion across all columns, then conversion speed is improved, but conversion accuracy deteriorates due to clock skew variations between columns
Solution Approach 1:
The patent divides the imaging sensor into multiple independent column processing units, each with its own local clock and analog-to-digital converter. This segmentation eliminates the clock skew problem that occurs when a single centralized clock is used, as each column operates independently with its own timing reference, thereby maintaining both high conversion speed and accurate measurement.
Solution Approach 2:
Each column processing unit is equipped with locally generated clocks and conversion circuitry tailored to its specific needs. This local quality approach ensures that each column has optimal timing characteristics without being affected by variations in other columns, resolving the contradiction between speed and accuracy by making the system adaptive to local conditions.
2Speed
If rapidly varying signals are used for analog-to-digital conversion, then conversion speed is improved, but power consumption increases and conversion errors occur
Solution Approach 1:
The patent employs periodic ramp signals for analog-to-digital conversion instead of continuous rapidly varying signals. The ramp signal increases linearly over time and is reset periodically, allowing conversion to occur at controlled intervals. This periodic approach maintains conversion speed while reducing power consumption compared to continuous high-frequency signal generation.
3Device complexity
If a single centralized analog-to-digital converter is used for all columns, then device complexity is reduced, but conversion accuracy deteriorates due to signal distribution issues
Solution Approach 1:
Instead of using a single centralized converter, the patent segments the conversion function into multiple distributed column processing units. Each unit handles conversion for its specific column independently, eliminating signal distribution issues that degrade accuracy while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent transitions from a single-dimension centralized conversion architecture to a multi-dimensional distributed architecture where conversion occurs independently in each column dimension. This dimensional change allows parallel processing that maintains accuracy while managing complexity through spatial distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster, more accurate analog-to-digital conversion with reduced power consumption and is insensitive to clock frequency variations, allowing for higher frequency operation and improved conversion efficiency.
Implementation Method 1
Impinging photons are converted into charges in the pixel array and are accumulated during a certain integration period
Implementation Method 2
A ramp signal is applied to each of the columns circuits. The ramp signal is distributed to all columns
Data Source
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AI summary
An analog-to-digital converter 130 generates an output digital value equivalent to the difference between two analog signals. The converter 130 forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock 110 is dedicated to the converter 130, or a sub-set of converters 130. A control stage 130 enables a first counter 151 based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter 130 can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters 130. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage.