Pixel Array Parasitic Capacitance Reduction
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Solution Overview
Problem
The color washout problem in liquid crystal display panels is not effectively addressed due to parasitic capacitances in the sub-pixel design, which degrade display quality by reducing the voltage difference between pixel electrodes.
Innovation Solution
The design includes sub-pixels with specific configurations of signal output and floating terminals, featuring openings that reduce parasitic capacitance, allowing for increased voltage differences between pixel electrodes, thereby improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sub-pixel is divided into main display region and sub-display region with different bias voltages, then the color washout problem can be overcome, but parasitic capacitances reduce the voltage difference between pixel electrodes, degrading display quality
Solution Approach 1:
The patent extracts and removes the parasitic capacitance elements (Cx1 and Cx2) from the circuit by redesigning the transistor connections. Specifically, the drain of the second thin film transistor is connected to the second pixel electrode without crossing over the first pixel electrode, and the drain of the third thin film transistor is connected to the first pixel electrode without crossing over the second pixel electrode, thereby eliminating the parasitic capacitances that were degrading the voltage difference and display quality.
Solution Approach 2:
The patent applies different bias voltages to different regions of the sub-pixel (main display region and sub-display region) by using separate pixel electrodes (first pixel electrode and second pixel electrode) with independent voltage control through the transistor network. This local differentiation of voltage conditions allows the main display region and sub-display region to operate with optimized voltage levels for their respective functions, overcoming the color washout problem while maintaining high display quality.
2Ease of manufacture
If the drain of the second thin film transistor crosses over the first pixel electrode to connect to the second pixel electrode, then the circuit connection is achieved, but parasitic capacitance Cx1 is generated between the drain and the first pixel electrode
Solution Approach 1:
The patent removes the harmful parasitic capacitance Cx1 by changing the routing of the drain of the second thin film transistor. Instead of allowing it to cross over the first pixel electrode (which would create parasitic capacitance), the drain is directly connected to the second pixel electrode through a path that does not involve crossing over the first pixel electrode, thereby extracting the parasitic capacitance element from the circuit while maintaining the necessary circuit connectivity.
3Ease of manufacture
If the drain of the third thin film transistor crosses over the second pixel electrode to connect to the first pixel electrode, then the circuit connection is achieved, but parasitic capacitance Cx2 is generated between the drain and the second pixel electrode
Solution Approach 1:
The patent extracts and removes the parasitic capacitance Cx2 by redesigning the connection path of the drain of the third thin film transistor. The drain is connected to the first pixel electrode through a direct path that does not cross over the second pixel electrode, thereby eliminating the parasitic capacitance element while maintaining the required circuit connectivity between the third transistor and the first pixel electrode.
Data Source
AI summary
A pixel array including a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixel is provided. Each of the sub-pixel arranged in the nth row includes a first switch, a second switch, a first pixel electrode, a second pixel electrode, and a third switch, wherein the first switch and the second switch are electrically connected to the nth scan line and the mth data line, the first pixel electrode is electrically connected to the first switch, the second pixel electrode is electrically connected to a signal output terminal of the second switch. The first pixel electrode has a first aperture above the signal output terminal. The third switch is electrically connected to the (n+1)th scan line and the second pixel electrode, and the second pixel electrode has a second aperture above a floating terminal of the third switch.