Pixel Array Substrate Recess Signal Lines RC Delay
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Solution Overview
Problem
Current display technologies face challenges with RC delay effects due to parasitic resistance and capacitance in pixel driving circuits, particularly in high-resolution and high-frame-rate displays, which affect display quality and require widening or thickening of signal lines, leading to issues like reduced pixel aperture ratio and substrate fragility.
Innovation Solution
The pixel array substrate incorporates insulation patterns with recess structures to reduce signal line resistance and increase the distance between signal lines and conductive patterns, enhancing charging and discharging capabilities while maintaining substrate stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the signal line is increased to reduce resistance, then the charging and discharging capability is improved, but the pixel aperture ratio is reduced
Solution Approach 1:
The signal line transitions from a planar two-dimensional structure to a three-dimensional structure by filling the recess structure with conductive material. This vertical dimensionality change allows the signal line to achieve lower resistance through increased effective cross-sectional area without expanding its horizontal footprint, thereby maintaining the pixel aperture ratio while improving charging and discharging capability.
2Reliability
If the thickness of the signal line is increased to reduce resistance, then the charging and discharging capability is improved, but the uniformity of the film surface decreases and substrate fragility increases
Solution Approach 1:
The signal line is segmented into multiple portions: a first portion on the first insulation layer and a second portion filling the recess structure in the second insulation layer. This segmentation allows each portion to maintain appropriate thickness independently, achieving low overall resistance without excessive thickness in any single layer, thereby preserving film surface uniformity and reducing substrate fragility.
Solution Approach 2:
Instead of uniformly increasing the thickness of the signal line across the entire structure, the invention uses the vertical dimension selectively by creating a recess structure only in specific regions. This localized three-dimensional configuration reduces resistance where needed while maintaining uniform film thickness in other areas, preventing substrate fragility.
3Loss of time
If the signal line is made wider to reduce parasitic resistance, then the RC delay effect is suppressed, but the pixel aperture ratio is lost
Solution Approach 1:
The invention addresses RC delay by utilizing the vertical dimension through the recess structure rather than expanding horizontally. The signal line's effective cross-sectional area is increased in the thickness direction, reducing parasitic resistance and thereby suppressing RC delay effects while keeping the horizontal dimensions small to preserve pixel aperture ratio.
Data Source
AI summary
A pixel array substrate including a substrate, multiple insulation patterns, multiple signal lines, and multiple pixel structures is provided. The insulation patterns are disposed on the substrate, and each has at least one recess structure. The signal lines are respectively disposed on the insulation patterns and are respectively filled in the at least one recess structure of one of the insulation patterns. The pixel structures are disposed on the substrate and are electrically connected to the signal lines. A pixel array substrate further including multiple conductive patterns is also disposed.