Pixel Array Scan Line Layout for Uniform Display Brightness
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Solution Overview
Problem
The capacitive coupling effect between scanning signal lines in narrow border or borderless display devices causes signal interference, affecting brightness and display quality.
Innovation Solution
A pixel array substrate design with interleaved first and second scan lines and balanced cross-capacitances across pairs of scan lines, ensuring uniform brightness by maintaining equal total cross-capacitances for each pair, and incorporating block selection lines and AND gate circuits to control signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If narrow border or borderless design is adopted to increase screen-to-body ratio, then display area is increased, but capacitive coupling effect between scanning signal lines causes signal interference and affects display quality
Solution Approach 1:
The scan lines are divided into multiple pairs, with each pair consisting of a first scan line and a second scan line. These pairs are arranged in an interleaved manner, segmenting the scanning signal transmission paths to reduce mutual interference and capacitive coupling effects while maintaining high display area coverage.
Solution Approach 2:
Different regions of the display panel are assigned different scan line pairs with optimized routing. The first and second scan lines in each pair are positioned to balance the number of cross-capacitances locally, ensuring uniform brightness and reducing signal interference in specific areas while maintaining overall high screen-to-body ratio.
2Area of stationary object
If multiple scan lines are arranged closely to increase display area, then screen-to-body ratio is improved, but uneven brightness occurs due to unequal cross-capacitances
Solution Approach 1:
Within each scan line pair, the first scan line and second scan line are positioned asymmetrically relative to the conductive lines, but the total number of cross-capacitances is balanced symmetrically. This asymmetric positioning with balanced total capacitance ensures uniform brightness across different pixel columns while maintaining high display area density.
Solution Approach 2:
The patent ensures that each pair of scan lines has equal total cross-capacitances, creating equipotential conditions for signal transmission. This balancing approach compensates for the capacitive coupling effects and maintains uniform brightness across the display panel, even with closely arranged scan lines.
3Area of stationary object
If scan lines are routed to connect different pixel columns, then display coverage is improved, but signal interference increases due to crossing conductive lines
Solution Approach 1:
The scanning signal transmission is segmented into multiple independent pairs of scan lines. Each pair is routed to connect different pixel columns, and the interleaved arrangement segments the signal paths to minimize mutual interference, maintaining reliable signal transmission across the entire display coverage area.
Solution Approach 2:
The patent employs a feedback mechanism where the number of cross-capacitances for each scan line pair is calculated and balanced. This feedback optimization ensures that signal transmission quality is maintained by adjusting the routing to achieve equal total cross-capacitances, thereby improving reliability while expanding display coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces uneven brightness and enhances display quality by minimizing capacitive coupling effects, resulting in uniform brightness across the display panel.
Implementation Method 1
the capacitive coupling effect between scanning signal lines may cause transmitted signals to interfere with each other
Data Source
AI summary
A pixel array substrate includes pixel circuits placed at a display area, first conductive lines placed at a first peripheral region, second conductive lines placed at a second peripheral region, and pairs of scan lines including a first scan line and a second scan line apiece. The first scan line is connected to the first conductive line, and extends to the display area for connecting a first pixel column. The second scan line is connected to the second conductive line, and extends to the display area for connecting a second pixel column. A sum of the number of cross-capacitances formed by the first scan line crossing the first conductive lines and the number of cross-capacitances formed by the second scan line crossing the second conductive lines are the number of total cross-capacitances, and the number of total cross-capacitances is the same for each pair of scan lines.