Pixel Array Substrate Shielding for Clock-Data Interference
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Solution Overview
Problem
Large-sized display panels face interference issues between clock and data line signals during long-distance transmission, affecting display quality.
Innovation Solution
A pixel array substrate design incorporating a shielding structure between clock and data lines, with direct current voltage signals provided to the shielding structure to reduce stray capacitance and mitigate interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If long-distance transmission is implemented for clock and data line signals in large-sized display panels, then the display area and coverage are improved, but signal interference and display quality deteriorate
Solution Approach 1:
A shielding structure is introduced as an intermediary element between the clock signal line and data line signal. This shielding structure, positioned in the second conductive pattern layer, acts as a mediator that blocks electromagnetic interference between the two signal types, allowing long-distance transmission to proceed without harmful interference while maintaining the large display area
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement of signals to a three-dimensional stacked architecture with multiple conductive pattern layers separated by dielectric layers. By stacking the clock signal line (first conductive pattern) and data line (third conductive pattern) in different layers with a shielding structure (second conductive pattern) in between, the patent eliminates interference while maintaining signal transmission functionality across the large display area
2Object-affected harmful factors
If shielding structure is added between clock and data lines, then signal interference is reduced, but device complexity increases
Solution Approach 1:
The shielding structure is merged with the existing multi-layer conductive pattern architecture. Instead of adding a completely separate shielding component, the patent integrates the shielding function into the second conductive pattern layer, which is part of the standard TFT array structure. This merging approach reduces complexity by utilizing existing structural elements for dual purposes (signal transmission and shielding)
Solution Approach 2:
The second conductive pattern layer serves multiple functions: it acts as a shielding structure to block interference between clock and data lines, while also being part of the overall signal transmission network. This multi-functionality reduces the need for additional dedicated shielding components, thereby limiting the increase in device complexity while achieving effective interference reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces mutual interference between clock and data signals, enhancing display quality by minimizing stray capacitance.
Implementation Method 1
a second conductive pattern (200) located on the first dielectric layer (I1) and includes a shielding structure (220) that is overlapped with the first branch clock signal line (112)
Data Source
AI summary
A pixel array substrate includes a substrate, a gate driver circuit, a first conductive pattern, a first dielectric layer, a second conductive pattern, a second dielectric layer, and a third conductive pattern. The first conductive pattern includes a first branch clock signal line which is electrically connected to the gate driver circuit. The first conductive pattern is located between the substrate and the first dielectric layer. The second conductive pattern is located between the first dielectric layer and the second dielectric layer and includes a shielding structure. The third conductive pattern is located on the second dielectric layer and includes a first clock signal line and a data line. The first branch clock signal line electrically connects the first clock signal line to the gate driver circuit and intersects the data line. The shielding structure is located between the data line and the first branch clock signal line.