Pixel Array ADC Using Single-Ramp Differential Conversion
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Solution Overview
Problem
Current analog-to-digital conversion techniques in imaging sensors face limitations in speed and accuracy due to the need for distributing counter signals across multiple ADC units and the requirement for counter direction changing circuitry, which can lead to conversion errors and increased semiconductor area requirements, especially in applications like Time Delay and Integration (TDI) where multiple exposure periods necessitate efficient accumulation of signal values.
Innovation Solution
The proposed solution involves an analog-to-digital converter that uses a single ramp cycle for both analog signals, allowing concurrent or sequential comparison, and employs a control stage with a first counter for integer clock cycles and a second counter for fractional cycles, eliminating the need for counter direction changes and separate adders, thereby improving conversion speed and reducing semiconductor area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If counter direction changing circuitry is used to perform analog-to-digital conversion, then the conversion can be performed using existing counter architecture, but the device complexity increases and conversion errors may occur
Solution Approach 1:
Instead of changing the counter direction to handle both reset and signal level conversions, the patent inverts the approach by always counting up from zero and using subtraction logic. The counter 31 consistently increments in the upward direction, and the digital difference is obtained by subtracting the signal level count from the reset level count, eliminating the need for direction changing circuitry.
Solution Approach 2:
The counter 31 is designed to perform multiple functions: it counts both the reset level and signal level conversions, generates overflow signals for both levels, and works with the same ramp signal for both measurements. This multi-functional design eliminates the need for separate counters or direction changing mechanisms.
2Productivity
If counter signals are distributed across multiple ADC units, then parallel conversion can be achieved, but conversion errors due to clock skew and counter delay variations increase
Solution Approach 1:
The patent combines the reset level conversion and signal level conversion into a single integrated process using one counter 31 per column. Both conversions share the same counter, the same ramp signal, and the same clock source, eliminating the distribution of counter signals across multiple ADC units and the associated clock skew and delay variations.
Solution Approach 2:
The patent uses feedback mechanisms where the overflow signals from both reset and signal level conversions are fed into OR gates 34a and 34b, which then control the enable signals for the counter. This feedback ensures synchronized operation and eliminates timing errors that would arise from distributed counter architectures.
3Duration of action of moving object
If separate storage registers and adders are used for digital domain accumulation in TDI applications, then multiple exposure periods can be accumulated, but the semiconductor area increases
Solution Approach 1:
The counter 31 serves multiple functions: it performs the analog-to-digital conversion for each exposure period and simultaneously acts as the accumulation register for Time Delay and Integration applications. By loading the counter with a load value representing the desired number of accumulations and using the enable logic to control counting during each exposure, the same counter hardware accumulates multiple exposure values without requiring separate storage registers and adders.
Solution Approach 2:
The counter 31 is self-sufficient in that it performs both the conversion function and the accumulation function. The counter automatically maintains the accumulated value across exposure periods by controlled reloading and continued counting, eliminating the need for separate dedicated accumulation hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and speed of analog-to-digital conversion by eliminating the need for counter signal distribution and direction changes, allowing for efficient accumulation of digital signal values across multiple exposure periods without additional hardware, particularly benefiting TDI applications by reducing semiconductor area and preventing image saturation.
Implementation Method 1
The ramp generator 20 produces a ramp signal which is sequentially compared with the analog signal levels
Implementation Method 2
The comparator 19 in each column compares the level of the input signal (V reset or V sig) against the gradually changing ramp signal
Implementation Method 3
The counter 17 is incremented in synchronism with the ramp signal such that, at any point in time, the counter 17 provides a digital representation of the analog value of the ramp signal
Data Source
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AI summary
An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.