Pixel Array Substrate Capacitance Ratio Compensation
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Solution Overview
Problem
Large-sized LCD devices face challenges in maintaining precise control over pixel storage capacitances and gate/drain capacitances due to overlay alignment errors and line-width deviations, leading to flicker and mura issues in the display image.
Innovation Solution
A pixel array substrate design where the capacitance ratio of pixel storage capacitance to gate/drain capacitance is maintained within a specific range, ensuring a constant feed-through voltage by adjusting the overlap areas and widths of electrodes, thereby compensating for process deviations and maintaining uniform image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a large-sized mask is used to fabricate large-sized LCD, then the display size is increased, but the overlay alignment error between metal layers increases
Solution Approach 1:
The patent changes the geometric parameters of the capacitor electrode structure, specifically designing it to span across the gate electrode in the first direction with a width ratio between 0.5 and 2.0 times the gate electrode width. This parameter optimization ensures that the pixel storage capacitance and gate/drain capacitance maintain a stable ratio despite overlay alignment errors, thereby resolving the contradiction between large display size and manufacturing precision.
2Volume of moving object
If the exposure range is increased for large-sized mask, then the display size is increased, but the line-width error in patterning process increases
Solution Approach 1:
The patent optimizes the capacitor electrode width parameter to be between 0.5 and 2.0 times the gate electrode width, which compensates for line-width errors during the patterning process. This geometric parameter adjustment ensures that even with exposure range increases and resulting line-width deviations, the capacitance ratio remains stable, maintaining display quality while enabling larger display sizes.
3Reliability
If the capacitance ratio of pixel storage capacitance to gate/drain capacitance is not controlled, then the feed-through voltage varies, but controlling it requires precise process control
Solution Approach 1:
The patent establishes a specific geometric parameter relationship where the capacitor electrode width is designed to be between 0.5 and 2.0 times the gate electrode width. This parameter optimization inherently controls the capacitance ratio without requiring complex precise process control, as the geometric relationship naturally compensates for process variations, thereby ensuring feed-through voltage consistency while maintaining manufacturing feasibility.
Solution Approach 2:
The capacitor electrode structure is designed to automatically compensate for process deviations through its geometric configuration. The electrode spanning across the gate electrode with optimized width ratio self-regulates the capacitance ratio, making the system self-correcting against manufacturing variations without requiring external intervention or complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures consistent feed-through voltages across pixels, preventing flicker and mura by maintaining a constant proportion of capacitances, even with process deviations, resulting in a uniform and stable LCD image.
Implementation Method 1
the voltage level of the pixel electrode in each pixel (P10A, P10B, P10C . . . ) is maintained by a liquid crystal capacitance CLC
Implementation Method 2
a gate/drain capacitance CGD is formed in an overlapping area of each drain electrode and the corresponding gate electrode
Implementation Method 3
the rotation angles of liquid crystal molecules are changed mainly by the magnitude of an applied electric field
Implementation Method 4
As the magnitude of the electric field applied to the liquid crystal molecules depends on a voltage difference between a pixel electrode of each pixel and a common electrode
Data Source
AI summary
A pixel array substrate including a substrate, a first patterned conductive layer, a second patterned conductive layer, and pixel electrodes is provided. The first patterned conductive layer has scan lines and gate electrodes. The second patterned conductive layer has data lines, source electrodes, drain electrodes, and capacitor electrodes. The data lines and the scan lines define many pixel areas. Many pixel storage capacitances CST is formed between the capacitor electrodes and the first patterned conductive layer. Many gate/drain capacitances CGD is formed in an overlapping area of the drain electrodes and gate electrodes. A liquid crystal capacitance CLC is formed above each pixel electrode. In at least one pixel area, the capacitance ratio of CST and CGD is α, the capacitance ratio of CLC and CST is β, and the ratio of a first deviation of CST and a second deviation of CGD is within the range of α(1+β)(1±50%).