Pixel Array Substrate 3D Storage Capacitor Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-resolution liquid crystal displays face issues with reduced aperture ratio and storage capacitor size due to limited circuit layout space, leading to flicker and crosstalk problems.
Innovation Solution
A pixel array substrate design that includes a substrate with a planarization layer, active device, and conductive layers positioned on the side surfaces of the planarization layer's opening to increase storage capacitor size, along with a color filter layer and spacer to enhance display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of display panels is increased continuously, then the visual experience is improved, but the aperture ratio is reduced and the storage capacitor size is reduced
Solution Approach 1:
The conductive layers are extended onto the side surfaces of the planarization layer opening, transitioning from a two-dimensional planar layout to a three-dimensional structure. This vertical extension utilizes the side surface area to increase storage capacitor size without occupying additional horizontal space, thereby maintaining aperture ratio while supporting higher resolution.
Solution Approach 2:
The first and second conductive layers are positioned within and on the side surfaces of the planarization layer opening, nesting the capacitor structure within the existing pixel structure. This nested arrangement increases storage capacitor area without expanding the overall pixel footprint, enabling higher resolution displays to maintain sufficient capacitor size.
2Measurement precision
If the resolution of display panels is increased continuously, then the visual experience is improved, but the storage capacitor size is reduced
Solution Approach 1:
The storage capacitor structure extends vertically onto the side surfaces of the planarization layer opening, utilizing the third dimension to increase capacitor volume. The first conductive layer on the bottom surface and the second conductive layer on the side surface create a three-dimensional capacitor structure that increases storage capacity without expanding the horizontal footprint.
Solution Approach 2:
The storage capacitor is segmented into multiple conductive layers (first conductive layer and second conductive layer) positioned at different locations (bottom surface and side surface). This segmentation allows the capacitor to utilize both planar and vertical space, increasing total storage capacity while maintaining compact dimensions suitable for high-resolution displays.
3Productivity
If the circuit layout space is limited, then the pixel density is increased, but the storage capacitor size is reduced
Solution Approach 1:
The conductive layers extend onto the vertical side surfaces of the planarization layer opening, utilizing vertical space to increase storage capacitor volume. This three-dimensional configuration allows sufficient capacitor size to be achieved within the limited horizontal circuit layout space, enabling higher pixel density without compromising capacitor performance.
4Productivity
If the storage capacitor size is reduced, then the pixel density is increased, but flicker and crosstalk issues occur
Solution Approach 1:
The extended conductive layers on the side surfaces create additional storage capacitor area that compensates for the reduced horizontal space. This three-dimensional capacitor structure maintains sufficient storage capacity to prevent flicker and crosstalk, ensuring display quality reliability even at high pixel densities.
Data Source
AI summary
A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.