Pixel Array Substrate Narrow Bezel Design via Demultiplexer Segmentation
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Solution Overview
Problem
As display panel resolution increases, the number of driving signal lines and peripheral traces reduces the layout space in the peripheral area, making it impossible to achieve a narrow bezel design in display panels used for VR, AR, and MR applications.
Innovation Solution
A pixel array substrate design with a substrate, signal lines, pixels, demultiplexers, and connecting lines where the demultiplexers are disposed in different regions and the connecting lines have higher electrical resistivity than the signal lines, allowing for a reduced peripheral area and increased design margin for bonding pads and circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display panel is increased, then the visual experience and realism are improved, but the number of driving signal lines increases, reducing the layout space in the peripheral area
Solution Approach 1:
The display area is divided into a first row region and a second row region, with different demultiplexers assigned to each region. This segmentation allows independent routing of signal lines to different pixel row regions, reducing the number of peripheral traces needed and freeing up peripheral area layout space while maintaining high display resolution.
Solution Approach 2:
The patent utilizes the vertical dimension by dividing the display area into multiple row regions and placing demultiplexers at different vertical positions. This dimensional approach allows signal lines to be distributed more efficiently across the panel, reducing peripheral area congestion caused by high resolution requirements.
2Device complexity
If demultiplexers are used to reduce the number of peripheral traces, then the number of traces is reduced, but the demultiplexers themselves occupy part of the peripheral area
Solution Approach 1:
Instead of using a single demultiplexer that would occupy a large peripheral area, the patent segments the demultiplexer function into multiple smaller demultiplexers distributed across different row regions. This segmentation reduces the peripheral area occupied by demultiplexer circuits while maintaining the trace reduction benefit.
Solution Approach 2:
The patent moves demultiplexer circuits from the peripheral area into the display area by distributing them across different row regions vertically. This dimensional relocation reduces peripheral area occupation while the segmentation into multiple demultiplexers maintains the benefit of reduced peripheral traces.
3Length of stationary object
If the peripheral area is reduced to achieve narrow bezel design, then the bezel width is reduced, but the design margin for bonding pads and circuits is reduced
Solution Approach 1:
The patent relocates demultiplexer circuits from the peripheral area into the display area across different row regions. This dimensional relocation enables narrower bezels while preserving peripheral area for bonding pads and circuits, thus maintaining manufacturing precision and design margin.
Solution Approach 2:
By segmenting the display area into multiple row regions with distributed demultiplexers, the patent creates more flexible routing options for signal lines. This segmentation allows optimized signal line routing that maintains adequate design margins for bonding pads and circuits even with reduced bezel width.
Data Source
AI summary
A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first demultiplexer, a second demultiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first demultiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second demultiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first demultiplexer. The second connecting line is electrically connected to the second demultiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.