Pixel Array Substrate Via Alignment for Aperture Ratio
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Solution Overview
Problem
The challenge in improving the resolution of display panels, such as fringe-field switching (FFS) mode display panels, is that the distance between the pixel electrodes and common electrodes occupies valuable display area, limiting further resolution enhancement due to the need for preventing short circuits.
Innovation Solution
A pixel array substrate design with a specific via structure in the insulating layers allows for self-aligned patterning of the common electrode openings, increasing the area available for the common electrode and preventing short circuits by using a connection portion of the pixel electrode that is narrower than the via, ensuring accurate alignment and avoiding contact with the common electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between pixel electrodes and common electrodes is increased to prevent short circuits, then reliability is improved, but the aperture ratio deteriorates
Solution Approach 1:
The patent changes the spatial arrangement from a planar layout to a three-dimensional stacked structure. The common electrode is positioned above the pixel electrode with vertical separation, allowing electrical isolation without horizontal spacing. This dimensional transition enables the electrodes to be closer in the plane while maintaining insulation through the vertical insulating layer structure.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between the common electrode and pixel electrode. These insulating layers act as mediators that provide electrical isolation, allowing the electrodes to be positioned closer together while preventing short circuits. The intermediary insulating structure enables reduced spacing without compromising reliability.
2Area of stationary object
If the distance between pixel electrodes and common electrodes is decreased to increase aperture ratio, then area is improved, but manufacturing precision deteriorates due to alignment difficulty
Solution Approach 1:
The patent forms the insulating layers and defines the opening positions before positioning the pixel electrodes. This preliminary structuring establishes fixed reference points that guide subsequent electrode placement, ensuring precise alignment without requiring high-precision direct positioning between electrodes. The preparatory insulating structure acts as a template for accurate electrode formation.
Solution Approach 2:
The insulating layers serve as intermediary reference structures that facilitate precise alignment. By establishing fixed insulating patterns first, the patent creates stable reference points that simplify the alignment process for subsequent electrode formation, reducing the manufacturing precision requirements compared to direct electrode-to-electrode alignment.
3Area of stationary object
If the opening width of common electrode is increased to increase aperture ratio, then area is improved, but the risk of short circuit increases
Solution Approach 1:
The patent transitions from horizontal separation to vertical separation for preventing short circuits. The common electrode opening can be widened in the horizontal plane to increase aperture ratio, while electrical isolation is maintained through the vertical insulating layer structure. This dimensional change allows independent optimization of electrode area and insulation without the trade-off present in planar designs.
Solution Approach 2:
The insulating layers act as intermediary barriers that enable the common electrode opening to be widened without increasing short circuit risk. The insulating material fills the space between the electrodes, allowing the common electrode area to be maximized while maintaining reliable electrical isolation through the intermediary insulating structure.
Data Source
AI summary
A pixel array substrate including pixel units is provided. Each of the pixel units includes a thin film transistor, a first insulating layer disposed on the thin film transistor, a common electrode disposed on the first insulating layer, a second insulating layer covering the common electrode, and a pixel electrode disposed on the second insulating layer. The first insulating layer includes a first via. The common electrode includes an opening and connects to the first via. The second insulating layer includes a second via and connects to the opening and the first via. The pixel electrode connects to the thin film transistor through the second via, the opening and the first via. The first via has two first sides opposite to each other and the opening has two third sides opposite to each other are aligned. A fourth side of the opening is not connected to the first via and the second via.