Pixel Array Substrate Transfer Line Integration
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Solution Overview
Problem
The challenge in display device design is to minimize the frame width while maintaining high aperture ratio and manufacturing yield, as existing solutions occupy layout area with transfer lines and increase circuit complexity, affecting the pixel array substrate's performance.
Innovation Solution
The pixel array substrate design interlaces data and gate lines with transfer lines, where pixels have overlapping and non-overlapping regions with transfer lines, and includes an insulation layer with through holes for electrical connections, allowing for efficient gate line grouping and timing control to improve aperture ratio and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If transfer lines are used to electrically connect gate lines to gate driving circuit, then the gate driving circuit can be disposed on the lower side of the display region, but the transfer lines occupy the layout area of the display region and increase circuit complexity
Solution Approach 1:
The patent merges the transfer line function with the gate line function by making the transfer line and gate line substantially coincident in the overlapping region. This integration reduces the number of separate conductive structures and simplifies the overall circuit layout while maintaining the ability to drive pixels in different scanning directions.
Solution Approach 2:
The transfer line is designed to serve multiple functions: it acts as both a transfer line for vertical signal transmission and as a gate line for horizontal pixel control in the overlapping region. This multi-functionality reduces the total number of conductive lines required and decreases circuit complexity.
2Ease of operation
If transfer lines are used to electrically connect gate lines to gate driving circuit, then the gate driving circuit can be disposed on the lower side of the display region, but the transfer lines occupy the layout area of the display region
Solution Approach 1:
The transfer line and gate line are merged into a substantially coincident structure in the overlapping region, eliminating the need for separate parallel lines and reducing the total area occupied by conductive structures in the display region.
Solution Approach 2:
The patent utilizes the vertical stacking of conductive layers to resolve the area occupation issue. By routing transfer lines in the vertical direction in one layer and gate lines in the horizontal direction in another layer, the design achieves three-dimensional space utilization that reduces the two-dimensional layout area requirement.
3Area of stationary object
If transfer lines overlap with pixel electrodes, then the aperture ratio can be improved, but parasitic capacitance increases
Solution Approach 1:
The transfer line width is varied in different regions: it is wider in regions where overlap with pixel electrodes is minimal or beneficial for aperture ratio, and narrower in regions where overlap would excessively increase parasitic capacitance. This local variation optimizes the balance between aperture ratio and parasitic capacitance.
Solution Approach 2:
The patent changes the geometric parameters of the transfer line, specifically the line width, as a function of position along the transfer line. This parameter variation allows the design to optimize the trade-off between aperture ratio (benefiting from wider lines) and parasitic capacitance (reduced by narrower lines in overlapping regions).
Data Source
AI summary
A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.