Pixel Array Transistor Orientation for LCD Flicker Reduction
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Solution Overview
Problem
Interlaced flicker occurs in existing liquid crystal display devices due to differences in parasitic capacitance and transistor arrangement directions, leading to inconsistent voltages on common electrodes and display quality issues.
Innovation Solution
Transistors in the pixel array are arranged in the same direction, ensuring consistent parasitic capacitance and voltage levels, with pixel units connected to scan and data lines in a specific pattern to reduce flicker and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors in pixel units are arranged in different directions to achieve zigzag data line control, then the display device can achieve dot inversion through column inversion, but parasitic capacitance differences cause inconsistent voltages on common electrodes leading to interlaced flicker
Solution Approach 1:
The patent applies local quality by making transistors in even rows have opposite orientation to adjacent odd rows, creating localized directional differences that enable dot inversion through column inversion while maintaining overall display stability through controlled parasitic capacitance management
Solution Approach 2:
The patent uses inversion by orienting transistors in even rows opposite to those in odd rows, allowing the system to achieve dot inversion functionality through column inversion of data signals while managing the parasitic capacitance effects through this symmetrical arrangement
2Adaptability or versatility
If transistors are arranged in different directions in adjacent rows, then column inversion can achieve dot inversion, but manufacturing complexity increases and parasitic capacitance varies
Solution Approach 1:
The patent implements local quality by restricting directional changes to specific even rows while keeping odd rows uniform, enabling polarity inversion capability in targeted areas without requiring complete redesign of the entire transistor array, thus balancing manufacturing ease with functional capability
3Productivity
If data lines control pixel units in a zigzag pattern, then fewer data lines are needed, but parasitic capacitance differences cause voltage inconsistency on common electrodes
Solution Approach 1:
The patent applies local quality by implementing zigzag data line control only in even rows while maintaining separate control in odd rows, achieving data line efficiency in specific regions while preserving voltage consistency through localized application of the zigzag pattern
Solution Approach 2:
The patent uses segmentation by dividing the pixel array into even and odd row groups with different control patterns, allowing zigzag data line control to be applied selectively to even rows while odd rows use traditional control, thereby maintaining voltage consistency while achieving data line efficiency
Data Source
AI summary
A pixel array includes: pixel units, data lines quantitatively corresponding to the number of columns N of the pixel units, and scan lines quantitatively corresponding to the number of rows of the pixel units, wherein transistors in the pixel units are arranged in the same direction; the pixel units in the same row are connected to the same scan line; the pixel units in each column and in odd rows are connected respectively to corresponding one of the data lines; the pixel units in each column and in even rows are connected respectively to corresponding one of the data lines; and the pixel units in the nth column and in even rows and the pixel units in the n+1 th column and in odd rows are connected to the same data line, where n=1, 2, . . . , N.