Pixel-Based Rule Checking for Curvilinear IC Layouts
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Solution Overview
Problem
Existing optical lithography processes face challenges in accurately transcribing critical dimensions of circuit patterns onto substrates, especially as feature sizes approach the resolution limit of exposure tools.
Innovation Solution
The implementation of a pixel-based rule checking method that performs rasterization operations to generate pixel-based definitions from contour-based definitions, allowing for optimal rule checks on layouts with curvilinear edges by assigning processing threads to pixels and dynamically generating edges for rule checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If optical lithography is used to manufacture circuit patterns, then the manufacturing process can be standardized and scaled, but the accuracy of critical dimensions deteriorates as feature sizes approach the resolution limit of exposure tools
Solution Approach 1:
The patent applies preliminary action by performing optical proximity correction (OPC) on the mask design before the actual lithography exposure. This pre-processing step modifies the mask patterns to compensate for expected distortions, thereby improving the accuracy of critical dimensions in the final manufactured circuit while maintaining the scalability of the optical lithography process
2Reliability
If conventional rule checking methods are used on layouts with curvilinear edges, then the design rules can be verified, but the checking accuracy deteriorates due to insufficient representation of curvilinear features
Solution Approach 1:
The patent applies curvature by representing curvilinear edges in the layout using multiple collinear pixels that approximate the curved geometry. This approach enables conventional rule checking methods to accurately verify design rules on curvilinear features by transforming them into a discrete pixel representation that preserves the essential geometric characteristics for measurement and validation
Data Source
AI summary
Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).