Pixel Block Imaging Circuit With In-Wiring Addition
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Solution Overview
Problem
Conventional imaging devices face challenges in reducing circuit size for adder circuits and downsizing transistors while maintaining high breakdown voltage requirements, which hinders the downscaling of transistors and efficient photoelectric conversion.
Innovation Solution
The imaging device incorporates a pixel block configuration with N first circuits, N second circuits, and a third circuit, where each first circuit converts incident light into an electrical signal, and the second circuits multiply and binarize the signal, with the results being added through a wiring connected to the third circuit, utilizing metal oxide transistors for reduced circuit size and high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional logic circuits are used for addition operation in binary neural networks, then addition can be performed, but the circuit size cannot be reduced
Solution Approach 1:
The patent changes the operating parameters by using binary-weighted capacitors instead of conventional binary representation, allowing addition operations to be performed through capacitor merging rather than complex logic circuits. This parameter change enables reduced circuit size while maintaining addition capability.
Solution Approach 2:
The patent substitutes conventional electronic logic circuit addition with a physical capacitor merging mechanism. Instead of using logic gates for addition, the system uses capacitive charge merging, which naturally performs addition through parallel connection of capacitors, thereby reducing circuit complexity.
2Volume of moving object
If transistors are downscaled to reduce device size, then device density increases, but maintaining high breakdown voltage becomes difficult
Solution Approach 1:
The patent employs a composite transistor structure combining silicon-based semiconductors with high-k dielectric materials for the gate insulator. This composite approach allows downscaled transistor dimensions while maintaining high breakdown voltage through the superior electrical properties of the high-k material.
Solution Approach 2:
The patent applies different material properties to different regions of the transistor structure. The channel region uses silicon for good carrier mobility, while the gate insulator uses high-k material for high breakdown voltage, and the source/drain regions are optimized separately. This local optimization allows downsizing while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the circuit size of the adder circuit and enables the use of downscaled transistors with high breakdown voltage, enhancing the imaging device's performance and reliability.
Implementation Method 1
Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal
Data Source
AI summary
An imaging device with an arithmetic function in which the circuit size is reduced is provided. The imaging device includes a plurality of pixel blocks. Each of the pixel blocks includes N (N is an integer greater than or equal to 1) first circuits, N second circuits, and a third circuit. Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal and has a function of outputting a first signal that is obtained by binarizing the electrical signal to the second circuit. Each of the second circuits has a function of outputting a second signal that is obtained by multiplying the first signal by a weight coefficient to a third circuit. When the N second signals are output to a wiring electrically connected to the third circuit, addition is performed. The first circuit includes a transistor, and an OS transistor is preferably used as the transistor.