Pixel Structure Bump Design for W/L Ratio and Aperture
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Solution Overview
Problem
In TFT-LCDs, increasing the channel width to enhance the W/L ratio of thin film transistors leads to a significant increase in device layout area, resulting in a loss of aperture ratio, which is not effectively addressed by current technologies.
Innovation Solution
A pixel structure is designed with a bump on the substrate, featuring a unique outer profile that allows the photoresist material to automatically separate into two portions, enabling the formation of a patterned photoresist layer without exposure and development processes, thereby increasing the W/L ratio without reducing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel width is increased to enhance the W/L ratio, then the turned-on current increases, but the device layout area increases significantly, resulting in loss of aperture ratio
Solution Approach 1:
The invention introduces a three-dimensional bump structure on the substrate, transforming the traditional planar two-dimensional layout into a three-dimensional configuration. The semiconductor layer is formed on both the top surface and side surfaces of the bump, creating a vertical channel structure that increases the channel width without expanding the horizontal device layout area, thus resolving the contradiction between increased turned-on current and maintained aperture ratio
Solution Approach 2:
The semiconductor layer is nested on the bump structure, utilizing the vertical space above and around the bump to accommodate the channel region. This nesting approach allows the channel to extend vertically along the bump's side surfaces, effectively increasing the channel width while keeping the horizontal footprint compact, thereby improving turned-on current without sacrificing aperture ratio
Data Source
AI summary
A pixel structure includes a scan line, a data line, a bump, an active device, and a pixel electrode electrically connected to the active device. The active device includes a gate, a semiconductor layer, a gate insulation layer between the gate and the semiconductor layer, a source, and a drain. The bump has a top surface and side surfaces in periphery of the top surface. The gate covers the bump and electrically connects the scan line. The semiconductor layer is on the top surface and the side surfaces. The source is on at least one of the side surfaces, in contact with the semiconductor layer, and electrically connected to the data line. The drain is on the top surface and in contact with the semiconductor layer, and the drain does not cover the semiconductor layer on a corner section of the bump between the top surface and the side surfaces.