Pixel Capacitor Overlap With Bank for Higher Aperture Ratio

The capacitor is moved from the same layer as transistors to a different layer (either above or below), utilizing vertical stacking to resolve the spatial conflict. This dimensional transition allows the capacitor and transistors to coexist without requiring excessive lateral spacing, thereby maintaining both manufacturing simplicity and aperture ratio.

The capacitor structure is nested within or alongside the transistor structure by forming capacitor electrodes within the same pixel area using overlapping regions. This nesting approach allows both components to share the same spatial footprint without interfering with each other's electrical characteristics, thus preserving aperture ratio while simplifying the manufacturing process.

The capacitor is positioned in a different layer (above or below the transistor layer) to exploit vertical space. This allows the capacitor electrodes to overlap in the vertical dimension without increasing lateral footprint, thereby achieving sufficient capacitance value while maintaining aperture ratio and minimizing parasitic capacitance with adjacent conductors.

The capacitor structure utilizes composite electrode configurations with multiple metal layers and insulating materials to achieve high capacitance density. By employing high-k dielectric materials and optimized electrode stacking, sufficient capacitance is obtained within a compact area, preventing aperture ratio degradation and reducing parasitic effects.