Pixel Compensation Capacitor Layout for Display Color Smear Reduction
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Solution Overview
Problem
Compact and high-resolution display devices face luminance issues such as color smear due to hysteresis, which affects the efficient spatial arrangement and driving of transistors, capacitors, and wirings, leading to image quality degradation.
Innovation Solution
The implementation of compensation capacitors in pixel driving circuits that stabilize voltage by increasing the on-bias voltage of driving transistors, with parallel-connected capacitors and controlled electrode areas to adjust light emission for each color pixel, reducing light emission delay and deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compensation capacitors are added to stabilize voltage and increase on-bias voltage of driving transistors, then color smear and blurring are reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the compensation capacitor structure: voltage stabilization, on-bias voltage enhancement, and light emission timing control are all achieved through the capacitor's electrode configurations and connections to the power line, reducing the need for separate components
Solution Approach 2:
The compensation capacitor serves multiple purposes: it stabilizes voltage across the pixel circuit, increases the on-bias voltage of driving transistors to reduce hysteresis effects, and controls light emission timing for different color pixels, making it a multi-functional component that addresses several issues simultaneously
2Reliability
If electrode areas of compensation capacitors are controlled to adjust on-bias voltage for each color pixel, then light emission timing is synchronized, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different electrode area sizes to different color pixels (Red, Green, Blue) to provide tailored on-bias voltage compensation for each color's specific hysteresis characteristics, with each pixel's compensation capacitor electrodes sized locally to match its requirements
Solution Approach 2:
The invention changes the capacitance parameter by varying electrode areas to adjust the on-bias voltage magnitude for each color pixel, using parameter adjustment (electrode area) as the primary means to control light emission timing and synchronize color output
3Reliability
If parallel-connected compensation capacitors are used to further increase on-bias voltage, then hysteresis compensation is enhanced, but device complexity increases
Solution Approach 1:
The patent merges multiple compensation capacitors in parallel configuration to achieve enhanced hysteresis compensation while sharing common electrodes and power line connections, reducing the need for completely separate circuit paths for each capacitor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces color smear and blurring by stabilizing voltage and controlling light emission timing across color pixels, thereby enhancing image quality and reducing luminance deviations.
Implementation Method 1
compensation capacitors in the pixel driving circuits of the display may compensate for hysteresis by voltage stabilization
Implementation Method 2
luminance problems in compact and high resolution display devices, such a color smear, may be caused by hysteresis
Implementation Method 3
a power line electrically connected to the first electrode layer and the third electrode layer
Data Source
AI summary
A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.