Pixel Capacitor Structure for Display Aperture Ratio and Storage Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increasing resolution in LCDs leads to challenges such as flickering, low color contrast, and cross-talk due to the need to reduce pixel size and storage capacitor area, which compromises the aperture ratio.
Innovation Solution
A semiconductor structure for a display device featuring a pixel capacitor with a bottom electrode, interlayer dielectric, top electrode, capacitor dielectric layer, and transparent electrode, where the transparent electrode connects to the drain electrode plug, allowing for increased storage capacitance without reducing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the plane area of the storage capacitor is reduced to increase the aperture ratio, then the aperture ratio is improved, but the storage capacitance decreases
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional structure by forming a pixel electrode that extends vertically from the substrate surface. The pixel electrode is formed to have a height greater than the thickness of the common electrode, creating a stepped configuration that increases the effective overlapping area between electrodes without increasing the planar footprint, thus maintaining aperture ratio while increasing capacitance.
Solution Approach 2:
The patent embeds the pixel capacitor structure within the pixel electrode formation process. The pixel electrode is formed in the same planarization layer that contains the TFT structures, and the capacitor electrodes are positioned within the vertical space created by the elevated pixel electrode, effectively nesting the capacitor function within the existing pixel structure.
2Measurement precision
If the pixel size is reduced to increase resolution, then the resolution is improved, but the storage capacitance and aperture ratio deteriorate
Solution Approach 1:
By forming the pixel electrode with significant height (greater than common electrode thickness), the patent creates a vertical dimension for capacitance accumulation. This allows the capacitor effective area to be decoupled from the planar pixel size, enabling high resolution with maintained capacitance in smaller pixels.
Solution Approach 2:
The patent changes the geometric parameters of the pixel electrode, specifically its height relative to the common electrode, to optimize the capacitance-to-area ratio. The pixel electrode height is controlled to be greater than the common electrode thickness, creating an optimized electrical field distribution that increases capacitance without increasing planar dimensions.
3Area of stationary object
If the storage capacitor area is reduced to maintain aperture ratio, then the aperture ratio is maintained, but display performance deteriorates due to flickering and low color contrast
Solution Approach 1:
The vertical elevation of the pixel electrode creates additional capacitance through increased overlapping area with the common electrode, providing sufficient charge storage capacity to prevent flickering and maintain color contrast while keeping the planar aperture ratio high.
Solution Approach 2:
The pixel electrode is formed with elevated height before final pixel electrode patterning, preliminarily establishing the capacitance-enhancing geometry. This preliminary structural configuration ensures adequate charge storage capacity is built into the device architecture before subsequent processing steps.
Data Source
AI summary
A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.