Pixel Circuit Capacitor Layering for Display Capacitance Control
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Solution Overview
Problem
The display device of Patent Literature 1 faces challenges in optimizing capacitance due to the gate electrode of the polysilicon-containing transistor being covered by an insulation film that also serves as a dielectric film of the capacitive element.
Innovation Solution
The display device incorporates a pixel circuit with transistors of different structures, where the dielectric film of the capacitive element is disposed in a different layer than the interlayer insulation films, allowing for separate optimization of capacitance without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode of the polysilicon-containing transistor is covered with an insulation film that also serves as a dielectric film of the capacitive element, then the manufacturing process is simplified, but the capacitance optimization becomes difficult
Solution Approach 1:
The patent divides the dielectric film into two separate layers: a first dielectric film covering the gate electrode of the polysilicon-containing transistor, and a second dielectric film serving as the dielectric film of the capacitive element. This segmentation allows independent optimization of each dielectric film's thickness and material properties, enabling precise capacitance control while maintaining manufacturing simplicity through sequential formation processes.
Solution Approach 2:
The patent introduces a vertical layering dimension by stacking the first and second dielectric films at different heights. The second dielectric film is positioned at a higher level than the first dielectric film, creating a multi-level structure that enables independent capacitance optimization without interfering with the gate electrode coverage function of the first dielectric film.
2Quantity of substance
If the dielectric film is made thicker to increase capacitance, then the capacitance value increases, but the pixel circuit area increases
Solution Approach 1:
The patent transitions from a single-layer dielectric structure to a multi-layer stacked structure, utilizing the vertical dimension to increase capacitance. By stacking the first and second dielectric films, the total capacitance is enhanced through increased dielectric volume without expanding the horizontal footprint of the pixel circuit, thus maintaining compact area while achieving higher capacitance values.
3Area of stationary object
If the dielectric film is made thinner to reduce pixel circuit size, then the area is reduced, but the capacitance optimization becomes limited
Solution Approach 1:
The patent segments the dielectric structure into multiple thin layers rather than using a single thick layer. Each dielectric film can be optimized for minimal thickness while maintaining adequate capacitance contribution. The cumulative capacitance of multiple thin stacked layers achieves the required total capacitance value within a compact pixel circuit area.
Solution Approach 2:
The patent compensates for reduced individual layer thickness by increasing the number of layers in the vertical stack. The multi-layer configuration provides cumulative capacitance that equals or exceeds what would be achieved by a single thick layer, enabling area reduction without sacrificing capacitance optimization capability.
Data Source
AI summary
A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.