Pixel Capacitor Layout for Faster CMOS Image Sensor Readout
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Solution Overview
Problem
In imaging devices, large capacitive elements can lead to increased parasitic capacitance with signal lines, delaying control signals and reducing imaging speed due to their extensive area occupation, which overlaps with signal lines in plan view.
Innovation Solution
The configuration includes a semiconductor substrate with pixels that have a photoelectric converter, a transistor with a gate electrically coupled to a signal line, and a capacitive element, where at least part of the transistor overlaps the capacitive element in plan view, and the capacitive element does not overlap the entire width of the signal line, minimizing parasitic capacitance through strategic layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitive element is made large to increase capacitance value, then the capacitance function is improved, but the parasitic capacitance with signal lines increases and imaging speed decreases
Solution Approach 1:
The patent applies dimensionality change by stacking the capacitive element in a different layer (second wiring layer) above the signal line (first wiring layer), separating them in the vertical dimension while maintaining electrical function. This reduces parasitic capacitance in the planar view while preserving the required capacitance value through the stacked configuration.
Solution Approach 2:
The patent segments the pixel structure into multiple wiring layers, placing the capacitive element and signal line in separate layers. This segmentation allows the capacitive element to achieve its function without occupying excessive planar area that would cause parasitic capacitance with signal lines.
2Quantity of substance
If the capacitive element occupies large area to achieve required capacitance, then the capacitance function is improved, but the signal line control is delayed due to overlap
Solution Approach 1:
The patent resolves the time delay issue by moving the capacitive element to a different vertical layer, reducing its planar overlap with the signal line. This dimensional separation minimizes parasitic capacitance coupling while maintaining the capacitive function, thereby reducing signal propagation delay.
3Area of stationary object
If the capacitive element is positioned to overlap the signal line for compact layout, then the area efficiency is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent achieves compact layout while reducing parasitic capacitance by utilizing the vertical dimension. The capacitive element is stacked above the signal line in a different wiring layer, creating a compact three-dimensional arrangement that minimizes planar overlap and associated parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed imaging by reducing parasitic capacitance and minimizing signal delay, thus enhancing the imaging device's performance.
Implementation Method 1
a photoelectric converter that converts light into signal charges
Data Source
AI summary
An imaging device includes: a semiconductor substrate; a plurality of pixels arrayed in a first direction on the semiconductor substrate; and a first signal line positioned above the semiconductor substrate. Each of the plurality of pixels includes: a photoelectric converter that converts light into signal charges; a transistor that includes a gate electrically coupled to the first signal line; and a capacitive element. In a first pixel of the plurality of pixels, at least a part of the transistor overlaps the capacitive element in plan view, and the capacitive element does not overlap the entire width of the first signal line in plan view.