Pixel Capacitor Layout With Vertical Stacking for Stable Display Voltage
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Solution Overview
Problem
Existing display devices face challenges in sufficiently securing the capacitance of capacitors within pixels, which affects the performance and efficiency of the display.
Innovation Solution
The display device incorporates a specific configuration of transistors and capacitors, including a first and second capacitor defined by conductive patterns and insulating layers, with overlapping electrodes and connection electrodes through contact holes, to enhance capacitor capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor configurations are used in pixels, then device complexity is reduced, but capacitor capacitance is insufficient
Solution Approach 1:
The patent implements a nested capacitor structure where a first capacitor and a second capacitor are combined within a single pixel circuit. The first capacitor is formed using the gate electrode of the first transistor and a first conductive pattern, while the second capacitor uses the first conductive pattern and a second conductive pattern. This nesting approach allows two capacitors to occupy overlapping spatial regions, effectively doubling the capacitance without proportionally increasing the pixel area or overall device complexity.
Solution Approach 2:
The patent utilizes the thickness direction (vertical dimension) of the display panel to increase capacitance. By stacking insulating layers and conductive patterns in multiple levels, the capacitor electrodes overlap in the thickness direction, creating three-dimensional capacitor structures. This dimensional transition from planar to vertical stacking allows sufficient capacitance to be achieved within the constrained pixel area without significantly increasing lateral dimensions.
2Reliability
If capacitor capacitance is increased, then display performance is improved, but pixel area increases
Solution Approach 1:
The first and second capacitors are nested within the same pixel circuit, with their electrodes overlapping in planar and vertical dimensions. The first conductive pattern serves as a shared element between both capacitors, allowing them to be compactly arranged without requiring separate dedicated areas for each capacitor, thus maintaining small pixel area while achieving sufficient total capacitance.
Solution Approach 2:
The patent transitions from two-dimensional planar capacitor布局 to three-dimensional stacked structures by utilizing the thickness direction. Multiple insulating layers and conductive patterns are stacked vertically, with capacitor electrodes overlapping in the vertical dimension. This allows the capacitor volume to be increased without proportionally increasing the pixel footprint area, effectively decoupling capacitance from planar area.
Data Source
AI summary
A pixel of a display device includes a light emitting element, a first transistor, a second transistor, a first capacitor, and a second capacitor. A gate electrode of the first transistor is disposed under the first insulating layer, and the gate electrode of the first transistor defines the first electrode of the first capacitor. A first conductive pattern defining a second electrode of the first capacitor and a first electrode of the second capacitor is interposed between a first insulating layer and a second insulating layer. A second conductive pattern defining a second electrode of the second capacitor is interposed between the second insulating layer and a third insulating layer. A second electrode of the second transistor is electrically connected to the first conductive pattern.