Pixel Circuit With Carrier Trapping for Refresh-Rate Uniformity
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Solution Overview
Problem
Existing light emitting display devices face challenges in maintaining uniform light emitting characteristics when operating frequencies vary, leading to inconsistencies in display quality.
Innovation Solution
The display device incorporates a pixel structure with specific transistor and capacitor configurations, including a carrier trapping induction signal that adjusts its level during different frames to maintain uniform light emission, and a panel driver that controls these signals to optimize display performance across varying frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency is varied to improve productivity, then the display refresh rate increases, but the light emitting characteristics become non-uniform
Solution Approach 1:
The patent applies a carrier trapping induction signal during a holding frame before the emission period to preliminarily trap carriers in the light emitting element. This preliminary action ensures that when the emission period begins at different frequencies, the carriers are already properly positioned, maintaining uniform light emitting characteristics regardless of the operating frequency variations.
Solution Approach 2:
The patent changes the voltage level of the carrier trapping induction signal based on the operating frequency. During the holding frame, the signal level is adjusted (first level during write frame, second level during carrier trapping induction period) to optimize carrier trapping efficiency at different frequencies, thereby maintaining consistent light emitting characteristics across varying refresh rates.
2Productivity
If the frame rate is increased to improve productivity, then the display updates faster, but the carrier distribution becomes non-uniform
Solution Approach 1:
The patent introduces a holding frame between the write frame and the emission period, during which a carrier trapping induction signal is applied. This preliminary action redistributes carriers uniformly before the emission period begins, ensuring consistent carrier distribution even when the frame rate increases and time for carrier distribution becomes more critical.
3Productivity
If the emission period is shortened to improve productivity, then the power consumption decreases, but the light emission uniformity deteriorates
Solution Approach 1:
The patent applies the carrier trapping induction signal during the holding frame before the emission period. This preliminary carrier trapping ensures that carriers are already uniformly distributed and ready for emission, allowing the emission period to be shortened without compromising light emission uniformity, thereby improving overall emission efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and improved display quality by stabilizing light emission characteristics even when operating frequencies change, enhancing the overall performance of the display device.
Implementation Method 1
a first capacitor connected between a carrier trapping induction line, to which a carrier trapping induction signal is applied, and a first node
Implementation Method 2
a light emitting display device displays an image by using a light emitting diode that generates light through the recombination of electrons and holes
Data Source
AI summary
A display device includes a display panel including a pixel. The pixel includes a light emitting element, a first capacitor connected to a first node, a second capacitor connected between a second node and a voltage line, a first transistor connected to the first node, the second node, and a third node, a second transistor connected between the third node and the first node, a third transistor connected between the second node and a data line, a fourth transistor connected between the second node and the voltage line, a fifth transistor connected between the third node and the light emitting element, and a sixth transistor connected between the light emitting element and a reference voltage line.