Pixel Circuit Layout for High-Resolution Displays With Less Afterimage

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Solution Overview

Problem

High-resolution display apparatuses face challenges with pixel granularity perception, afterimage phenomena, high power consumption, wide bezels, and large size, particularly in devices like HMDs, which diminish immersion and display quality.

Innovation Solution

A display apparatus design incorporating a pixel structure with multiple transistors and capacitors, including a back gate and specific wiring configurations, utilizing metal oxide transistors with low off-state current, and employing a frame period where light-emitting devices are in a non-lighting state to reduce afterimages and enhance display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the resolution of the display apparatus is increased to reduce pixel granularity perception, then the display quality is improved, but the area of each pixel decreases which reduces the number of elements that can be provided in the pixel

Engineering Contradiction:
Improvedisplay resolutionVSAvoidnumber of elements per pixel
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The pixel circuit is divided into multiple functional blocks: a first transistor and first capacitor for storing drive signals, a second transistor and second capacitor for storing selection signals, and a third transistor for controlling the light-emitting device. This segmentation allows each element to perform a specific function efficiently, enabling high-resolution displays with optimized circuit layouts that fit within reduced pixel areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs multi-layer stacking of transistors and capacitors in the vertical dimension to reduce the planar footprint. By arranging circuit elements in multiple layers rather than only on a plane, the circuit can accommodate more functional elements within the constrained pixel area, supporting higher resolution without proportionally increasing the number of planar elements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-generated harmful factors

If the light-emitting device is turned off completely to reduce afterimages, then display quality is improved, but the transition time increases and may cause display artifacts

Engineering Contradiction:
Improveafterimage phenomenonVSAvoidtransition time between states
Core Design Contradiction:
Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The display apparatus employs periodic scanning of pixel circuits in a matrix pattern, where each pixel is sequentially selected and updated. This periodic action allows the light-emitting device to be turned off after a controlled period, enabling the phosphor to decay and reduce afterimages while maintaining synchronized updates that prevent display artifacts.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The selection signal is applied to the second transistor in advance to prepare the pixel circuit for the upcoming light-emitting phase. This preliminary action ensures that the pixel is ready to respond immediately when the drive signal is applied, reducing transition time and preventing artifacts while still allowing complete turn-off to minimize afterimages.

Inventive Principle:
Principle #10Preliminary action

3Area of stationary object

If the bezel width is reduced to improve display-to-device ratio, then the display area increases, but the space for driver circuits and other components decreases

Engineering Contradiction:
Improvedisplay areaVSAvoidspace for driver circuits
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The driver circuits are implemented using three-dimensional stacked transistors and capacitors that utilize the vertical dimension. This allows the driver circuits to occupy minimal planar space while maintaining full functionality, enabling the bezel to be reduced and more display area to be achieved within the same device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pixel circuits and driver circuits share common structural elements and fabrication processes. The same stacked transistor and capacitor structures used in pixel circuits are also employed in driver circuits, merging the design approaches to reduce overall device complexity and allow for reduced bezel widths.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves high-resolution displays with reduced afterimages, low power consumption, narrow bezels, and compact size, improving overall display quality and user immersion.

Implementation Method 1

achieves increased field-effect mobility by stacking a plurality of oxide semiconductor layers, containing indium and gallium in an oxide semiconductor layer serving as a channel

Methodology Applied
Scientific EffectField-effect mobility: Conduction (electrical)

Implementation Method 2

A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS20260013356A1Display Apparatus And Electronic Device
Publication Date: 2026.01.08 SEMICON ENERGY LAB CO LTD
  • US20260013356A1 patent drawing
  • US20260013356A1 patent drawing
  • US20260013356A1 patent drawing

AI summary

A display apparatus with high display quality is provided. A high-resolution display apparatus is provided. The display apparatus includes a plurality of pixels, and the pixels each include a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor. A gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. One frame period of each of the pixels includes a period in which the first transistor and the fourth transistor are each in a conduction state.