Pixel Circuit Timing for Afterimage-Reduced Display Panels
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Solution Overview
Problem
Existing display devices face challenges in achieving improved display quality, particularly in reducing instantaneous afterimages and enhancing pixel performance through efficient pixel circuit design.
Innovation Solution
The display device incorporates a pixel circuit with multiple transistors and capacitors, including a first transistor with a back-gate electrode, and a specific timing sequence of scan and emission control signals to optimize pixel initialization and emission intervals, reducing afterimages and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pixel circuit is used, then the device complexity is low, but instantaneous afterimages occur and display quality deteriorates
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks with dedicated transistors: a first transistor for current control, a second transistor for data writing, a third transistor for compensation, a fourth transistor for emission control, and a fifth transistor for reference voltage control. Each transistor handles a specific function, allowing precise control over pixel operations to eliminate afterimages while maintaining manageable complexity through functional modularity.
Solution Approach 2:
The circuit performs preliminary initialization of the light emitting element before data writing and emission. The first initialization interval sets up the pixel state, followed by compensation for threshold voltage variations, then data writing occurs. This sequential preliminary preparation ensures the pixel is properly conditioned before actual emission, preventing afterimage effects.
2Reliability
If multiple transistors and capacitors are added to reduce afterimages, then display quality improves, but the pixel circuit area increases
Solution Approach 1:
The storage capacitor and reference voltage control are merged into a unified structure where the fifth transistor controls the reference voltage line connection to the storage capacitor. This integration allows the circuit to perform multiple functions (data storage and reference voltage management) within a compact area, reducing the overall pixel circuit footprint while maintaining afterimage reduction capabilities.
Solution Approach 2:
The pixel circuit operates through periodic intervals: first initialization interval, compensation interval, second initialization interval, and emission interval. Each interval activates specific transistors in sequence, allowing the same hardware components to perform different functions at different times. This temporal multiplexing reduces the need for additional dedicated components, thereby minimizing pixel area.
3Reliability
If specific timing sequences of scan signals are used, then pixel performance is optimized and afterimages are reduced, but the control signal complexity increases
Solution Approach 1:
The control signals dynamically activate different transistor groups during different intervals. The scan signal selectively turns on the second transistor during the data write interval, the third transistor during the compensation interval, and the fourth and fifth transistors during initialization intervals. This dynamic switching allows a single pixel circuit to handle multiple operations sequentially, optimizing performance without requiring permanently active complex circuitry.
Solution Approach 2:
The compensation interval uses feedback mechanisms where the third transistor adjusts the gate electrode voltage based on threshold voltage variations detected during operation. This feedback loop compensates for device variations and maintains consistent pixel performance across different conditions, reducing afterimages through adaptive control rather than static complex circuit design.
Data Source
AI summary
Disclosed is a display device including a display panel including a light emitting element and a pixel circuit connected to the light emitting element, wherein the pixel circuit includes a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second power line, a second transistor connected between the second electrode of the first transistor and a data line to receive a write scan signal, a third transistor connected between the first node and the first electrode of the first transistor to receive a compensation scan signal, a storage capacitor connected between the first node and the second power line, and a fourth transistor connected between the storage capacitor and the second power line to receive a first emission control signal.