Pixel Circuit Initialization Layout for Black Voltage Suppression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Display devices face challenges in reducing back voltage corresponding to black gradation and preventing bright spot defects due to current leakage in pixels.

Innovation Solution

The display device incorporates a pixel circuit with a driving transistor and switching transistors, including a first and second initialization operation controlled by the same gate signal, which initializes the gate and source/drain electrodes of the driving transistor to bypass accumulated charge, reducing black voltage and preventing current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single initialization operation is performed in conventional display devices, then the manufacturing process remains simple, but black voltage cannot be effectively reduced and bright spot defects occur due to charge accumulation

Engineering Contradiction:
Improveimage qualityVSAvoidinitialization operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The initialization operation is divided into two distinct sections: a first initialization section that initializes the gate electrode, and a second initialization section that initializes the source/drain electrodes. This segmentation allows each initialization operation to target specific charge accumulation problems, effectively reducing black voltage and preventing bright spot defects while maintaining manufacturing feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first initialization operation is performed in advance during the first initialization section before the light emitting operation begins. This preliminary initialization of the gate electrode prevents charge accumulation that would otherwise cause black voltage issues during subsequent operations, thereby improving image quality proactively

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the same gate signal controls both initialization operations, then the control circuit remains simple, but precise timing control becomes difficult

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidinitialization timing precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The same gate signal is utilized in a periodic manner to control both the first and second initialization operations at different time intervals. The gate signal activates the first switching transistor during the first initialization section, then activates the second switching transistor during the second initialization section. This periodic reuse of the gate signal simplifies the control circuit while the sequential timing ensures precise initialization of different electrodes

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250391358A1Display device and electronic device including the same
Publication Date: 2025.12.25 SAMSUNG DISPLAY CO LTD
  • US20250391358A1 patent drawing
  • US20250391358A1 patent drawing
  • US20250391358A1 patent drawing

AI summary

A display device includes: a pixel circuit and a light emitting element electrically connected to the pixel circuit, a gate driver outputting a gate signal, and a data driver outputting a data voltage. The pixel circuit includes a driving transistor including a first end of a first area, a second area electrically connected to a power voltage line configured to receive a driving voltage, a first channel area, and a portion of a first gate electrode overlapping the first channel area, a first switching transistor including a portion of a first upper active pattern on the first gate electrode and configured to receive an initialization voltage, and a portion of a first upper gate line configured to receive a first gate signal and overlapping the first upper active pattern, and a connection pattern on the first upper gate line and connecting the first upper active pattern and the first area.