Pixel Circuit CMOS Transistors High PPI Luminance Accuracy

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Solution Overview

Problem

As the Pixels Per Inch (PPI) increases in display devices, the pitch of the pixel circuit narrows, limiting the number of transistors and reducing luminance accuracy due to a decreased data voltage range, which is particularly challenging for virtual reality (VR) and augmented reality (AR) applications requiring high PPI and small area pixel circuits.

Innovation Solution

The pixel circuit design includes a light emitting element, driving transistor, compensation transistor, data write transistor, first and second light emission control transistors, storage capacitor, and hold capacitor, with some transistors being N-type and others P-type, forming CMOS transistors to minimize leakage current, reduce area, and compensate for threshold voltage, while the storage and hold capacitors distribute voltage to expand the data range and prevent light emission due to leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the PPI increases to achieve high resolution display, then the luminance accuracy decreases due to reduced data voltage range

Engineering Contradiction:
Improveluminance accuracyVSAvoidPPI
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the parameter of transistor type from conventional single-type to dual-type (N-type and P-type) to alter the electrical characteristics of the pixel circuit. This parameter change enables the circuit to maintain a wider data voltage range even at high PPI, thereby preserving luminance accuracy while achieving high pixel density.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the pitch is narrowed to achieve high PPI, then the number of transistors is limited reducing circuit functionality

Engineering Contradiction:
ImprovePPIVSAvoidnumber of transistors
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the functionality of multiple transistors into a compact dual-type transistor configuration. By combining N-type and P-type transistors in a shared pixel circuit, the design achieves enhanced functionality equivalent to more transistors while occupying less area, thus maintaining circuit complexity at acceptable levels despite narrowed pitch.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dimensional change by utilizing both N-type and P-type transistors operating in different electrical dimensions. This allows the circuit to perform multiple functions (compensation, driving, light emission control) within a reduced transistor count, effectively adding functional depth without increasing physical footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional transistor configuration is used, then leakage current increases reducing display quality

Engineering Contradiction:
Improvedisplay qualityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potentially harmful leakage current into a beneficial feature by using complementary N-type and P-type transistors that work together to suppress leakage. The dual-type configuration creates balanced electrical characteristics where each transistor type compensates for the other's weaknesses, transforming what would be a harmful effect into an advantage for display quality.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250104612A1Pixel circuit and display device including the pixel circuit
Publication Date: 2025.03.27 SAMSUNG DISPLAY CO LTD
  • US20250104612A1 patent drawing
  • US20250104612A1 patent drawing
  • US20250104612A1 patent drawing

AI summary

A pixel circuit includes a light emitting element including an anode electrode and a cathode electrode configured to receive a second power voltage, a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a compensation transistor including a gate electrode configured to receive a compensation gate signal, a first electrode configured to receive a ground voltage, and a second electrode connected to the third node, a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode connected to a data line, and a second electrode connected to the first node, a first light emission control transistor, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node, a storage capacitor, and a hold capacitor.