Pixel Circuit Threshold Voltage Compensation for Display Hysteresis
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Solution Overview
Problem
Display devices face challenges in maintaining image quality due to hysteresis characteristic changes in driving transistors, leading to issues like flicker and image deterioration, especially at varying frame frequencies.
Innovation Solution
The implementation of a pixel structure with specific transistor configurations and timing control, including n-type oxide semiconductor and p-type polysilicon semiconductor transistors, along with capacitors, to secure threshold voltage compensation time and prevent display quality deterioration. This involves a complex arrangement of transistors and capacitors connected between different power lines and scan lines, with precise control of scan and emission control signals to manage bias states and emission periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the frame frequency is decreased to reduce power consumption, then power consumption is reduced, but display quality deteriorates due to hysteresis characteristic changes in driving transistors
Solution Approach 1:
The patent applies preliminary action by introducing a compensation period before the emission period during which the driving transistor is biased to compensate for threshold voltage shifts. This preliminary biasing action prevents hysteresis-induced display quality deterioration before it occurs, enabling the system to operate at lower frame frequencies without sacrificing display quality.
Solution Approach 2:
The patent changes the parameter of threshold voltage compensation by dynamically adjusting the bias voltage applied to the driving transistor during the compensation period. This parameter change allows the system to counteract hysteresis effects and maintain stable display quality across varying frame frequencies while reducing power consumption.
2Reliability
If the frame frequency is increased to display high resolution or stereoscopic images, then image quality is improved, but compensation period is insufficient leading to hysteresis characteristic changes
Solution Approach 1:
The patent segments the timing cycle into distinct compensation period and emission period phases. By segmenting the frame period, the system can allocate dedicated time for threshold voltage compensation before emission, ensuring sufficient compensation even at high frame frequencies where the overall period is shorter.
Solution Approach 2:
The patent implements periodic action by repeatedly executing the compensation period followed by the emission period in each frame cycle. This periodic compensation ensures that hysteresis effects are continuously addressed, maintaining image quality stability across multiple frames even when operating at high frame frequencies.
3Device complexity
If a simple pixel structure is used, then device complexity is reduced, but hysteresis characteristic changes cause flicker and image deterioration
Solution Approach 1:
The patent applies multi-functionality by designing the compensation circuit to serve multiple purposes: it compensates for threshold voltage shifts, eliminates flicker, and maintains image quality stability. This universal compensation mechanism addresses multiple hysteresis-related issues simultaneously without requiring separate circuits for each function, thereby limiting the increase in device complexity.
Data Source
AI summary
A pixel includes a light emitting element, a first transistor connected between first and second nodes and that generates a driving current flowing from a first power line to a second power line through the light emitting element, a second transistor connected between a data line and the first node and turned on in response to a fourth scan signal, a third transistor connected between the second node and a third node corresponding to a gate electrode of the first transistor and turned on in response to a second scan signal, a fourth transistor connected between the third node and a third power line providing a third power voltage and turned on in response to a first scan signal, and a fifth transistor connected between the first and fourth nodes and turned on in response to a fifth scan signal.