Pixel Driving Circuit Layout for OLED Crosstalk Reduction
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Solution Overview
Problem
In OLED displays, parasitic capacitances between data signal lines and the gate or source of driving transistors cause uneven local brightness due to stronger coupling between the data signal line and the gate, leading to crosstalk issues.
Innovation Solution
The wire layout of the pixel driving circuit is optimized by adjusting the positioning of the data signal line relative to the gate and source of the driving transistor, reducing coupling by increasing the distance between the data signal line and the gate, and enhancing coupling between the data signal line and the source through an overlapping region with the power signal line, while preventing overlap with the scan signal line to minimize series capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data signal line is positioned close to the gate of the driving transistor, then the coupling between data signal line and gate is strong, but this causes stronger parasitic capacitance and voltage jump, leading to brightness unevenness and crosstalk
Solution Approach 1:
The patent applies local quality by creating different coupling conditions at different locations: the data signal line is positioned to have weak coupling (larger distance) with the gate to reduce parasitic capacitance, while maintaining strong coupling (overlapping region) with the power signal line at the source region. This spatially differentiated coupling strategy resolves the contradiction by locally optimizing the electromagnetic interaction characteristics.
Solution Approach 2:
The power signal line serves as an intermediary element that mediates the coupling between the data signal line and the source of the driving transistor. By introducing this intermediate conductor with a controlled overlapping region, the patent enhances the coupling strength between data line and source without requiring direct proximity, thus reducing parasitic capacitance with the gate while maintaining signal integrity at the source.
2Object-affected harmful factors
If the data signal line is positioned far from the gate of the driving transistor, then the parasitic capacitance is reduced, but the coupling between data signal line and source may be weakened
Solution Approach 1:
The power signal line acts as an intermediary that bridges the gap between the data signal line and the source. By positioning the data signal line to overlap with the power signal line in a controlled region, the patent uses the power line as a mediator to maintain strong coupling with the source even when the data line is positioned farther from the gate to reduce parasitic capacitance.
3Reliability
If the power signal line overlaps with the data signal line, then the coupling between power line and data line is enhanced, but this may increase device complexity
Solution Approach 1:
The patent merges the functions of multiple signal lines by creating an overlapping region where the power signal line and data signal line share the same spatial pathway. This merging approach allows the power line to serve dual purposes: providing power to the source while simultaneously acting as a coupling medium for the data signal, thereby enhancing signal coupling without proportionally increasing layout complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the difference between gate and source voltages, improving brightness stability and reducing crosstalk phenomena in OLED displays.
Implementation Method 1
parasitic capacitances between data signal lines and the gate or source of driving transistors cause uneven local brightness due to stronger coupling between the data signal line and the gate
Data Source
AI summary
Provided are a wiring structure of a pixel driving circuit, a display panel, and a display device. The wire layout includes: a first switching element, a second switching element and a driving transistor. A source electrode of the driving transistor is connected to a power signal line. The power signal line includes a first power signal line that is in a same direction as a data signal line, and the data signal line is arranged at a position of the first power signal line away from a gate electrode of the driving transistor.