Active-Matrix Pixel Circuit Layout for Crosstalk Reduction
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Solution Overview
Problem
In display devices using the active matrix method, crosstalk occurs due to a large current instantaneously flowing through power supplying lines during signal writing, causing brightness inconsistencies in adjacent pixels.
Innovation Solution
The display device incorporates sub-pixels with transistors of varying width-to-length ratios to distribute the current flow more evenly across power supplying lines, reducing instantaneous current peaks and minimizing crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal writing is performed using conventional transistors with uniform width-to-length ratios, then the manufacturing process is simple, but large current peaks flow through power supplying lines causing crosstalk and brightness inconsistency
Solution Approach 1:
The patent applies local quality by assigning different width-to-length ratios to writing transistors based on their specific positions and functions within the pixel circuit. Specifically, the writing transistor connected to the emission control line has a different W/L ratio than those connected to scanning lines, allowing optimized current control for emission timing without affecting other pixel operations uniformly
Solution Approach 2:
The patent changes the electrical parameters of writing transistors by varying their width-to-length ratios. This parameter modification allows different writing transistors to have different current driving capabilities, thereby distributing current peaks more evenly across power supplying lines and reducing crosstalk effects on adjacent pixels
2Object-generated harmful factors
If transistors with different width-to-length ratios are used to distribute current flow, then crosstalk is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by selectively applying different W/L ratios only to specific writing transistors based on their functional roles, rather than requiring all transistors to have precisely controlled unique dimensions. This localized differentiation reduces the overall manufacturing precision burden while still achieving current distribution goals
Solution Approach 2:
The patent modifies transistor parameters (W/L ratios) in a controlled manner with discrete values rather than continuous variations, making the parameter changes manufacturable with standard precision tolerances while still achieving effective current peak distribution across power lines
3Device complexity
If uniform transistor dimensions are used across all sub-pixels, then device complexity is low, but instantaneous current peaks cause brightness inconsistency in adjacent pixels
Solution Approach 1:
The patent applies local quality by differentiating writing transistor W/L ratios based on their specific positions and functions within the pixel circuit. Specifically, the writing transistor connected to the emission control line has a different W/L ratio than those connected to scanning lines, allowing optimized current control for emission timing without affecting other pixel operations uniformly
Solution Approach 2:
The patent changes the electrical parameters of writing transistors by varying their width-to-length ratios. This parameter modification allows different writing transistors to have different current driving capabilities, thereby distributing current peaks more evenly across power supplying lines and reducing crosstalk effects on adjacent pixels
Data Source
AI summary
A display unit includes sub-pixels that each have a light emitting element, a capacitor, a first transistor that writes a video signal potential to the capacitor, and a second transistor that provides a drive current to the light emitting element based on a voltage stored in the capacitor. Each first transistor has a channel width W and channel length L, such that a width to length ratio is W/L. The width to length ratio W1/L1 of one of the first transistors is different than a width-to-length ratio W2/L2 of at least one other of the first transistors.


