Pixel Circuit Topology for High-PPI Data Range Expansion
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Solution Overview
Problem
Display devices with high pixel density face challenges in maintaining luminance accuracy due to reduced data voltage range and restricted transistor count, which limits the number of signals and area available for pixel circuits.
Innovation Solution
A pixel circuit design incorporating a light emitting element, transistors, and capacitors that utilize specific signal activation periods and power voltage distribution to expand data range and minimize body effects, allowing for high pixel density and reduced transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel density is increased to achieve high PPI, then the pixel circuit area is reduced, but the number of transistors and signals that can be accommodated is restricted
Solution Approach 1:
The pixel circuit is segmented into multiple functional blocks with shared resources. Specifically, the circuit uses shared transistors (T1-T5) and shared capacitors (C1, C2) that serve multiple purposes across different time periods, reducing the total transistor count while maintaining high PPI requirements
Solution Approach 2:
Transistors and capacitors are designed to perform multiple functions across different time periods. For example, T2 and T3 provide data voltage during both first and second periods, while C2 stores data voltage and provides compensation. This multi-functionality reduces the overall component count, enabling high PPI implementation
2Measurement precision
If the pixel circuit area is reduced to accommodate high PPI, then the number of signals is restricted, but luminance accuracy deteriorates
Solution Approach 1:
The pixel circuit operates in multiple time periods (first period, second period, third period) with different signal activation patterns. During the first period, T2 and T3 are activated to provide data voltage. During the second period, T4 is activated to provide power voltage. This periodic operation allows the same components to handle multiple signals over time, maintaining luminance accuracy while reducing spatial requirements
Solution Approach 2:
Capacitor C2 is pre-charged with data voltage during the first period before the emission phase. This preliminary charging ensures that the data voltage is ready and stable before luminance display, maintaining accuracy without requiring additional signal lines or larger circuit area
3Reliability
If more transistors are added to maintain signal capability, then the pixel circuit area increases, but high PPI is compromised
Solution Approach 1:
Multiple signal functions are merged into shared components. Transistors T2 and T3 are shared for data voltage transmission during different periods. Capacitor C2 serves dual purposes: storing data voltage and providing compensation voltage. This merging reduces the total transistor count to 5 components while maintaining complete signal capability for high PPI displays
Solution Approach 2:
The pixel circuit uses dynamic control where transistors are activated and deactivated based on time period requirements. T2 and T3 are active during data writing periods, while T4 is active during emission periods. This dynamic operation allows the same physical components to handle different signal requirements at different times, maintaining reliability with fewer transistors
Data Source
AI summary
A pixel circuit may include a light emitting element, a first transistor configured to provide a driving current to the light emitting element, a first capacitor including a first electrode connected to a control electrode of the first transistor and a second electrode connected to a first electrode of the first transistor, a second capacitor including a first electrode connected to the control electrode of the first transistor and a second electrode, a second transistor configured to provide a data voltage to the control electrode of the first transistor in response to a write gate signal, and a third transistor configured to provide the data voltage to the second electrode of the second capacitor in response to the write gate signal.