Pixel Circuit Layout for High-Integration Display Control
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Solution Overview
Problem
There is a need for improved integration of pixels in high-resolution display devices to enhance their performance and efficiency.
Innovation Solution
A pixel structure is introduced that includes a first transistor connected between a first power line and a second node, a second transistor connected between the first and a third node, and a third transistor connected between the second and third nodes, along with a light-emitting element and capacitors, where the transistors are controlled by varying scan signals to optimize pixel operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of pixels is increased, then the resolution and performance of display devices are improved, but the complexity of pixel circuit design and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple transistor functions into a shared structure where the first transistor serves both as a driving transistor for the light-emitting element and as part of the switching network. The second and third transistors share the third node and cooperate to control signal routing, reducing the total number of independent components needed while maintaining high integration functionality.
Solution Approach 2:
The first transistor functions dually as a driving transistor that controls current to the light-emitting element and as a switching element in the pixel circuit network. The capacitors serve multiple purposes including signal storage, voltage level maintenance, and timing control, enabling a compact design that achieves high integration without proportionally increasing complexity.
2Reliability
If more transistors and capacitors are added to improve pixel functionality, then display performance is enhanced, but the area occupied by each pixel increases
Solution Approach 1:
The patent implements a nested arrangement where transistor components are positioned and interconnected in a compact hierarchy. The shared third node and overlapping signal paths allow multiple functional elements to occupy overlapping or adjacent spatial regions, effectively nesting functions within a minimized footprint that prevents linear area growth with increased functionality.
Solution Approach 2:
The circuit layout utilizes multi-layer interconnections and vertical stacking arrangements where components are positioned in different planar layers or vertical levels. This dimensional approach allows signals to route through multiple levels rather than requiring extensive lateral spacing, enabling high-density integration without proportionally increasing the pixel's planar area.
3Manufacturing precision
If multiple scan lines are used to control transistors, then pixel control precision is improved, but the complexity of signal routing and manufacturing precision requirements increase
Solution Approach 1:
The patent segments the pixel control into distinct phases managed by different scan lines: the second scan line controls the switching phase (second transistor), while the third scan line controls the signal routing phase (third transistor). This temporal and functional segmentation allows each scan line to be optimized for its specific control task, improving precision while simplifying the overall manufacturing process through modular control architecture.
Data Source
AI summary
A pixel includes a first transistor including a gate electrode connected to a first node, where the first transistor is connected between a first power line and a second node, a second transistor including a gate electrode connected to an i-th scan line, where the second transistor is connected between the first node and a third node, and i is an integer equal to or greater than 1, a third transistor including a gate electrode connected to a j-th scan line, the third transistor is connected between the second node and third node, and j is an integer different from i, and a light-emitting element connected between the second node and a second power line.