Pixel Circuit Layout for Multi-Frequency Display Testing
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Solution Overview
Problem
Existing display devices face challenges in operating at various frequencies and effectively testing the operation of internal circuits, which can affect image quality and reliability.
Innovation Solution
A pixel and display device configuration is introduced, incorporating specific transistor and capacitor arrangements that allow for operation at different frequencies and include a test mode for circuit testing, utilizing transistors connected to multiple scan lines and capacitors for efficient initialization and compensation, enabling both normal and test modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional pixel circuit configuration is used, then the circuit can operate at a fixed frequency, but it cannot operate at various operating frequencies
Solution Approach 1:
The pixel circuit incorporates a test transistor and multiple scan lines that enable dynamic reconfiguration of the circuit operation mode. By controlling the test transistor through different scan signals, the circuit can switch between normal display operation and test modes, allowing adaptation to various operating frequencies without permanent structural changes.
Solution Approach 2:
The test transistor is integrated into the existing pixel circuit structure, allowing the same circuit to serve dual purposes: normal display operation and test mode operation. The test transistor can function as part of the normal circuit or be activated for testing, providing multi-functionality without requiring separate dedicated test circuits.
2Reliability
If internal circuit testing is not implemented, then the device structure remains simple, but the reliability and image quality cannot be ensured
Solution Approach 1:
The pixel circuit performs self-testing through the integrated test transistor that can detect abnormalities in the light emitting element and other circuit components. The testing function is built into the pixel itself, eliminating the need for external testing equipment and reducing overall system complexity while maintaining high reliability.
Solution Approach 2:
The test function is merged with the normal display function by integrating the test transistor within the pixel circuit structure. This consolidation allows testing capabilities to be incorporated without adding separate external testing components, thereby maintaining structural simplicity while enhancing reliability.
3Adaptability or versatility
If multiple transistors and capacitors are added for test mode and multi-frequency operation, then operating frequency versatility and testing capability are improved, but leakage currents increase
Solution Approach 1:
Capacitors are used to pre-charge and store voltages at critical nodes before test mode or high-frequency operation begins. This preliminary charging action reduces the need for continuous current flow during operation, thereby minimizing leakage currents while maintaining the ability to operate at various frequencies.
Solution Approach 2:
The circuit design applies different transistor types (P-type and N-type) in specific locations based on their electrical characteristics. P-type transistors are used where low leakage is critical, while N-type transistors are used where high switching speed is needed. This localized optimization reduces overall leakage current while maintaining frequency versatility.
Data Source
AI summary
A pixel includes a light emitting element, a first transistor including a first electrode electrically connected to a first voltage line, a second electrode electrically connected to the light emitting element, and a gate electrode connected to a first node, a second transistor including a first electrode connected to a data line, a second electrode, and a gate electrode connected to a first scan line, a third transistor including a first electrode electrically connected to the first node, a second electrode connected to the second electrode of the first transistor, and a gate electrode connected to a second scan line, and a test transistor including a first electrode connected to the first electrode of the first transistor, a second electrode electrically connected to the second electrode of the second transistor, and a gate electrode connected to the second scan line.