Pixel Circuit Layout With Dual Capacitors for High-Resolution Displays
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Solution Overview
Problem
High-resolution display apparatuses face challenges with pixel granularity, afterimage phenomena, high power consumption, wide bezels, and large size, particularly in devices like HMDs, which diminish immersion and display quality.
Innovation Solution
A display apparatus design incorporating a pixel structure with specific transistor and capacitor configurations, including a back gate and metal oxide channels, and a driver circuit layout to manage pixel brightness and reduce afterimages, while maintaining high resolution and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the resolution of the display apparatus is increased, then the pixel granularity is reduced and display quality is improved, but the area of each pixel decreases and the number of elements that can be provided in the pixel is reduced
Solution Approach 1:
The patent merges the function of multiple transistors into a single transistor by using a stacked configuration where transistors are arranged vertically. This allows the pixel circuit to maintain high-resolution functionality while reducing the horizontal space required, thereby accommodating more elements within the reduced pixel area.
Solution Approach 2:
The patent transitions from a planar arrangement of transistors to a three-dimensional stacked configuration. By arranging transistors in multiple layers vertically, the design utilizes the vertical dimension to increase functional density without increasing the horizontal footprint, thus solving the space constraint in high-resolution pixels.
2Manufacturing precision
If the number of elements in the pixel is increased, then the display quality and functionality are improved, but the pixel area increases and the bezel width increases
Solution Approach 1:
The patent segments the pixel circuit into multiple functional blocks arranged in a stacked configuration. Each transistor and capacitor is divided into separate layers with specific functions (e.g., switching, storage, driving), allowing efficient space utilization and reducing the overall pixel area while maintaining full functionality.
Solution Approach 2:
The stacked transistor configuration enables multiple transistors to share common structures and layers, reducing redundant elements. For example, multiple transistors can share source/drain regions or gate electrodes, thereby decreasing the total number of discrete elements needed while maintaining the required circuit functionality.
3Manufacturing precision
If the pixel area is reduced, then the resolution is improved, but the number of elements such as transistors and capacitors that can be provided in the pixel is reduced
Solution Approach 1:
The patent implements a nested structure where smaller functional units are placed within larger structural frameworks. For example, capacitors are positioned within the overlapping regions of transistor layers, and control lines are routed through shared channels, maximizing the utilization of available space within the reduced pixel area.
Solution Approach 2:
By transitioning to a three-dimensional stacked architecture, the patent increases the functional capacity of each pixel without increasing its two-dimensional footprint. Multiple transistor layers are vertically stacked, allowing more elements to be packed into the same planar area, thus maintaining high resolution while accommodating sufficient circuit elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a high-resolution display with reduced afterimages, low power consumption, narrow bezels, and compact size, enhancing user immersion and display quality.
Implementation Method 1
A transistor using a metal oxide has field-effect mobility higher than that in the case where amorphous silicon is used
Implementation Method 2
a first capacitor, one electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor
Data Source
AI summary
A display apparatus with high display quality is provided. A high-resolution display apparatus is provided. The display apparatus includes a plurality of pixels, and the pixels each include a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor. A gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. One frame period of each of the pixels includes a period in which the first transistor and the fourth transistor are each in a conduction state.