CMOS Pixel Circuit Charge Transfer via Dynamic Voltage Control
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Solution Overview
Problem
CMOS image sensors face limitations in maximizing the sense node voltage, leading to incomplete charge transfer and reduced signal swing due to limited voltage swing on the sense node, which affects image quality and full well capacity.
Innovation Solution
The pixel arrangement includes a photodiode, reset transistor, transfer gate transistor, source follower transistor, and a capacitor, where the transfer gate voltage transitions through intermediate levels to enhance the sense node voltage during read operations, allowing for increased voltage on the node and improved charge transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sense node voltage is increased to improve charge transfer efficiency, then the charge transfer efficiency is improved, but the voltage swing on the sense node is limited which reduces the signal swing
Solution Approach 1:
The transfer gate voltage is dynamically adjusted through multiple stages: initially set to a first voltage level to turn off the transfer gate transistor, then increased to a second voltage level to maximize sense node voltage and improve charge transfer efficiency, and finally increased further to a third voltage level to turn on the transfer gate transistor for charge transfer. This dynamic voltage adjustment resolves the contradiction by optimizing the sense node voltage during different phases of operation.
Solution Approach 2:
The patent changes the voltage parameter of the transfer gate control signal through distinct voltage levels. The transfer gate voltage transitions from a first voltage level (transfer gate off) to a second voltage level (intermediate state maximizing sense node voltage) and then to a third voltage level (transfer gate on). This parameter change enables the sense node voltage to reach its maximum value during the intermediate state, improving charge transfer efficiency while maintaining control over the transfer gate transistor.
2Measurement precision
If the transfer gate voltage is increased to maximize sense node voltage, then the sense node voltage is maximized, but the transfer gate transistor cannot transfer charge effectively
Solution Approach 1:
The transfer gate voltage is applied periodically in distinct phases: first at a first voltage level to keep the transfer gate transistor off during integration, then increased to a second voltage level to maximize sense node voltage for readout, and finally increased to a third voltage level to enable charge transfer. This periodic action with distinct voltage levels resolves the contradiction by ensuring that charge transfer occurs only when the transfer gate voltage is at the appropriate level.
Solution Approach 2:
The transfer gate voltage dynamically transitions through multiple levels to achieve both objectives: it reaches a second voltage level that maximizes the sense node voltage for accurate measurement, then transitions to a third voltage level that enables effective charge transfer. This dynamic control allows the system to optimize for measurement precision and charge transfer productivity at different times in the operation cycle.
3Power
If the read operation duration is extended to allow voltage increases, then the voltage can be increased for charge transfer, but the period for voltage increase is shorter than the read operation period
Solution Approach 1:
The transfer gate voltage is pre-configured to transition through specific voltage levels at predetermined times during the read operation. The voltage is increased to the second level before charge transfer is needed to maximize sense node voltage, and then to the third level to enable charge transfer. This preliminary action ensures that voltage adjustments are made in advance and in a coordinated manner, fitting within the read operation time constraints.
Solution Approach 2:
The voltage adjustment follows a periodic sequence with distinct phases: the transfer gate voltage transitions from the first level to the second level, then to the third level, in a timed sequence during the read operation. This periodic action with predetermined timing ensures that voltage increases occur within the available time window, with the voltage adjustment period being shorter than the total read operation period, thus resolving the time constraint contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes the sense node voltage, enhancing charge transfer efficiency and signal swing, thereby improving image quality and extending the imaging range by optimizing voltage levels and capacitance configurations.
Implementation Method 1
at least one photodiode
Implementation Method 2
a capacitance coupled between the node and the pass control signal
Data Source
AI summary
A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.