Pixel Circuit Erasing Transistor for Parasitic Light
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Solution Overview
Problem
In organic EL displays using time-division gradation driving, the electrooptic element sometimes emits light at low brightness or as bright spots due to parasitic capacitance effects, making it difficult to control the light-emitting state accurately without increasing the number of power supplies or wiring.
Innovation Solution
The display device incorporates a pixel circuit design with a driving transistor, a writing transistor, and an erasing transistor, along with a capacitor, where the erasing transistor is connected between the gate terminal of the driving transistor and a control line, and the data writing potential is set to maintain the writing transistor in an OFF state during non-light-emitting conditions, preventing unnecessary light emission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate erasing transistor is provided for data erase function, then data erase capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the data write and data erase functions into a single transistor (the third transistor) by utilizing different potential combinations on control lines Wi and Ei. When Wi is high and Ei is low, the transistor performs data write; when Wi is low and Ei is high, the transistor performs data erase. This eliminates the need for separate write and erase transistors, reducing device complexity while maintaining full functionality.
Solution Approach 2:
The third transistor is designed to serve multiple functions: it acts as a data write transistor when control lines are configured with Wi high/Ei low, and as a data erase transistor when control lines are configured with Wi low/Ei high. This multi-functional design allows a single component to replace what would traditionally require two separate components.
2Device complexity
If parasitic capacitance effects are present, then device complexity is reduced, but light emission control precision deteriorates
Solution Approach 1:
The patent applies preliminary anti-action by using the capacitor to store charge and the control line potential combinations to preemptively counteract parasitic capacitance effects. The capacitor maintains the gate potential of the driving transistor stable during control line transitions, and the specific potential combinations (Wi high/Ei low for write, Wi low/Ei high for erase) are applied in advance to prevent unwanted light emission before parasitic capacitance can cause issues.
Solution Approach 2:
The capacitor in the pixel circuit serves as a cushioning element that absorbs voltage fluctuations and potential spikes caused by parasitic capacitance during control line switching. This beforehand cushioning protects the gate potential from sudden changes that would otherwise cause unintended light emission, allowing the system to tolerate parasitic capacitance effects without compromising light emission control precision.
Data Source
AI summary
An erasing TFT 13 is provided between a gate terminal of a driving TFT 11 and a control line Ei, and a gate terminal of the erasing TFT 13 is connected to the control line Ei. When performing data erase, a potential not lower than a sum of a potential of a power supply line Vp and a threshold voltage of the erasing TFT 13 is applied to the control line Ei before performing data write, and an organic EL element 15 is controlled to be in a non-light-emitting state. A high level potential applied to a control line Wi is a potential at which a writing TFT 12 is maintained in an OFF state when a potential applied to a data line Sj is a high level potential corresponding to the non-light-emitting state. Accordingly, it is possible to prevent electrooptic elements from emitting light unnecessarily along with changes of potentials of the control lines without increasing the number of power supply or wiring.