Pixel Circuit Frequency Division for Low-Power Static Displays
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Solution Overview
Problem
Existing display apparatuses face high power consumption when displaying static images or operating in always-on mode, necessitating a reduction in driving frequency to conserve energy.
Innovation Solution
A pixel circuit design that supports multiple divisions of driving frequency through a block control signal, allowing for differential power consumption based on image requirements, utilizing P-type and N-type transistors to manage writing and initialization operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the driving frequency is decreased to reduce power consumption, then energy efficiency is improved, but the display refresh capability and responsiveness deteriorate
Solution Approach 1:
The pixel circuit dynamically adjusts its operating mode between address period and self-scan period based on block control signals. During address period, the circuit operates at full functionality to receive new data; during self-scan period, it maintains display output with reduced operations, enabling adaptive power consumption based on actual display needs rather than fixed high-frequency operation
Solution Approach 2:
The display driver alternates between address period and self-scan period in a periodic manner. The block control signal enables the pixel circuit to switch between these periods, allowing the system to cycle through high-activity data writing phases and low-activity display maintenance phases, thereby reducing average power consumption while maintaining display functionality
2Use of energy by moving object
If the driving frequency is decreased for static images, then power consumption is reduced, but the ability to display dynamic content efficiently deteriorates
Solution Approach 1:
The pixel circuit incorporates dynamic control through the block control signal that adjusts circuit behavior based on display content requirements. The circuit can adapt between address period mode (for dynamic content updates) and self-scan period mode (for static image power saving), providing versatility across different display scenarios without sacrificing energy efficiency
Solution Approach 2:
The circuit changes its operational parameters based on the block control signal state. During address period, the circuit accepts data writing and performs compensation operations; during self-scan period, it maintains output with minimal operations. This parameter switching enables the same hardware to efficiently handle both static and dynamic display content with optimized power consumption for each mode
3Use of energy by moving object
If additional transistors are added to enable frequency division, then power consumption control is improved, but device complexity increases
Solution Approach 1:
The block control transistor serves multiple functions: it controls the connection between third and fourth nodes during address period, enables compensation transistor operation, and facilitates the switching between address and self-scan periods. By making this transistor multi-functional, the circuit achieves power consumption control without adding excessive complexity, as one transistor performs several critical control roles
4Manufacturing precision
If the block control transistor is turned on during address period, then data writing accuracy is improved, but power consumption increases
Solution Approach 1:
The block control transistor is activated only during the address period when data writing occurs, and turned off during self-scan period. This periodic activation ensures that the transistor and associated circuitry operate at full accuracy during data writing while remaining inactive during display maintenance, thereby achieving high data writing accuracy without continuous power consumption
Data Source
AI summary
A pixel circuit includes a driving transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node and configured to generate a driving current based on a voltage of the first node, a writing transistor configured to apply a data voltage to the second node in response to a write gate signal, a block control transistor configured to connect the third node and a fourth node in response to a block control signal, an initialization transistor configured to apply an initialization voltage to the third node in response to an initialization gate signal, a compensation transistor configured to connect the fourth node and the first node in response to a compensation gate signal and a light emitting element configured to emit light based on the driving current.