Pixel Circuit Gate Potential Maintenance for Low-Frequency Display Refresh
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Solution Overview
Problem
In existing display technologies, the potential of the gate of the drive transistor cannot be maintained during low-frequency image refresh, leading to poor image quality due to changes in drive current and screen flicker.
Innovation Solution
A pixel circuit with a drive module, light emission control modules, and data write modules is designed to maintain the gate potential of the drive transistor by writing global data voltages and data control voltages at specific times during the image refresh cycle, ensuring consistent drive current and reduced flicker.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low-frequency image refresh is used to reduce power consumption, then energy efficiency is improved, but gate potential cannot be maintained causing image quality deterioration
Solution Approach 1:
The pixel circuit is divided into multiple functional modules: drive module, first light emission control module, second light emission control module, first data write module, and second data write module. Each module performs a specific function, allowing independent optimization of power management and signal writing operations to maintain image quality during low-frequency refresh
Solution Approach 2:
The first data write module writes global data voltage to the gate node in advance during specific time periods before the light emission phase. This preliminary action ensures the gate potential is established and maintained before refresh occurs, preventing image quality deterioration even at low refresh frequencies
Solution Approach 3:
The circuit implements periodic writing of global data voltage and data control voltage at specific time periods within each refresh cycle. This periodic action synchronizes with the low-frequency refresh rate while ensuring gate potential is replenished regularly to maintain image quality without excessive power consumption
2Device complexity
If traditional single data write module is used to simplify circuit structure, then device complexity is reduced, but gate potential cannot be maintained during low-frequency refresh
Solution Approach 1:
The data writing function is segmented into two independent modules: first data write module for global data voltage and second data write module for data control voltage. This segmentation allows each module to be optimized for its specific function, improving gate potential maintenance while keeping each individual module relatively simple
Solution Approach 2:
The first data write module writes global data voltage that serves multiple purposes: establishing gate potential, maintaining potential during retention frames, and enabling low-frequency refresh. This multi-functional approach reduces the need for additional complex circuitry
3Use of energy by moving object
If gate potential is not maintained during retention frames, then power consumption is reduced, but drive current changes causing screen flicker
Solution Approach 1:
The gate potential is written in advance during specific time periods before the light emission phase and maintained during retention frames. This preliminary and sustained action ensures drive current stability throughout the entire refresh cycle, preventing screen flicker while optimizing power consumption through controlled potential maintenance
Solution Approach 2:
The first data write module continuously maintains the gate potential during retention frames by periodic writing, ensuring uninterrupted drive current flow to the light-emitting module. This continuous action prevents flicker while allowing the circuit to operate at low power during non-emission periods
Data Source
AI summary
A first data write module of a pixel circuit, in response to an effective potential of a first control signal, writes a global data voltage on a first global signal line to a gate node of a drive module in a write frame and at least one retention frame to increase the frequency of writing data or prolong the duration of writing data at the gate node of the drive module during a low-frequency image refresh. A second data write module of the pixel circuit, in response to an effective potential of a second control signal, writes a data control voltage on a data line to a control node in the write frame to enable the control node to have a control potential, and maintains the potential of the control node at the control potential in the retention frame.