Pixel Circuit Gate Signal Sharing for Narrow Bezel Displays
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Solution Overview
Problem
In light emitting display apparatuses, increasing resolution and power consumption pose challenges in reducing power consumption, particularly due to the need for more gate control signals at lower frequencies, which complicates the design of gate driving circuits and reduces the effectiveness of power savings, and makes it difficult to implement a narrow bezel.
Innovation Solution
The solution involves reducing the number of gate control signals needed for pixel driving circuits by sharing gate control signals between adjacent horizontal lines, thereby enabling a narrower bezel and decreased power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of gate control signals is increased to enhance image quality at low frequency driving, then image quality characteristic is improved, but device complexity and bezel width increase
Solution Approach 1:
The patent merges the control of emission control signals for adjacent horizontal lines by sharing a single gate control signal between two gate driving circuits. Specifically, the first gate driving circuit generates an emission control signal for a first horizontal line and shares it with the second gate driving circuit for a second horizontal line, thereby reducing the total number of gate control signals and circuit complexity while maintaining image quality
Solution Approach 2:
The gate control signal serves multiple functions by being shared across different gate driving circuits for adjacent horizontal lines. A single gate control signal controls emission for multiple horizontal lines simultaneously, making the gate driving circuit more versatile and reducing overall circuit complexity
2Reliability
If the number of gate control signals is increased to enhance image quality at low frequency driving, then image quality characteristic is improved, but power consumption increases
Solution Approach 1:
The patent combines the emission control for adjacent horizontal lines under shared gate control signals, reducing the total number of active circuits and signal lines. This merging approach directly reduces dynamic power consumption while maintaining the required image quality through coordinated control of shared signals
3Use of energy by moving object
If the frame rate is lowered to reduce power consumption, then power consumption decreases, but image quality characteristic deteriorates
Solution Approach 1:
The patent implements periodic emission control by alternating between first and second horizontal lines in a low-frequency driving scheme. The gate driving circuits periodically switch between controlling different horizontal lines using shared emission control signals, enabling power-efficient low-frequency operation while maintaining image quality through coordinated periodic updates
Solution Approach 2:
By merging the emission control of adjacent horizontal lines through shared gate control signals, the system can operate at lower frame rates with fewer active circuits, reducing power consumption while maintaining image quality through the coordinated periodic updating of shared control signals
Data Source
AI summary
A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.