Pixel Circuit Layout for Stable Driving Transistor Gate Voltage

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Solution Overview

Problem

Existing pixel circuits in display devices face issues with adverse effects on driving characteristics due to capacitors connected in series between the gate terminal of the driving transistor and the power voltage terminal, affecting the robustness and efficiency of light emission.

Innovation Solution

The pixel circuit is redesigned with a series connection of transistors and capacitors that include a first transistor controlled by a light-emission control signal, a driving transistor controlled by a gate signal, and additional transistors controlled by scan and initialization signals, allowing for improved voltage application and compensation, reducing adverse effects on the driving transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If capacitors are connected in series between the gate terminal of the driving transistor and the power voltage terminal, then voltage storage and compensation are improved, but driving characteristics and light emission robustness deteriorate

Engineering Contradiction:
Improvevoltage storage and compensationVSAvoidadverse effects on driving characteristics
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The harmful capacitors connected in series between the gate terminal and power voltage terminal are removed from the circuit. This extraction eliminates the adverse effects on driving characteristics while preserving the essential voltage storage and compensation functions through alternative circuit configurations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The voltage storage and compensation functions are segmented into separate circuit elements: the first capacitor stores voltage at the first node, the second capacitor stores voltage at the second node, and the third capacitor provides compensation. This segmentation allows each capacitor to perform its function independently without the harmful series connection effects.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a simple transistor configuration is used, then device complexity is reduced, but voltage control precision and current stability deteriorate

Engineering Contradiction:
Improvetransistor configurationVSAvoidvoltage control precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

Multiple transistors (first, second, third, fourth, and driving transistors) are merged into a coordinated circuit configuration where each transistor performs a specific function: switching, voltage application, compensation, and current control. This combination achieves precise voltage control and stable current while maintaining reasonable device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The third capacitor provides feedback compensation to the driving transistor, ensuring stable voltage levels and consistent current control. This feedback mechanism maintains manufacturing precision without requiring overly complex transistor configurations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260051292A1Pixel, display device including the pixel, and electronic appratus including the pixel
Publication Date: 2026.02.19 SAMSUNG DISPLAY CO LTD
  • US20260051292A1 patent drawing
  • US20260051292A1 patent drawing
  • US20260051292A1 patent drawing

AI summary

A pixel includes a first transistor connected between a first power voltage terminal and a first node and turned on and off by a first light-emission control signal, a driving transistor connected in series with the first transistor and a light-emitting element and turned on and off by a signal applied to a gate terminal of the driving transistor, a second transistor connected between a data line and a second node connected to the gate terminal of the driving transistor, and turned on and off by a scan signal, a first capacitor connected between the first power voltage terminal and the first node, and a second capacitor connected between the first node and the second node.