Pixel Circuit Dynamic Gate Voltage Control for Display Reliability
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Solution Overview
Problem
Current pixel circuits in display substrates face challenges in simultaneously meeting the driving requirements of different refresh modes, particularly due to the inability to dynamically control gate voltage when switching between modes, which affects the reliability of the display apparatus.
Innovation Solution
The pixel circuit is designed with a first node control sub-circuit, a second node control sub-circuit, a light emitting control sub-circuit, and a drive sub-circuit, which include transistors and capacitors to stabilize node voltages and dynamically adjust signals based on different driving modes, allowing for simultaneous operation in multiple refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pixel circuit uses a fixed reference voltage for gate control, then the circuit structure is simple, but it cannot dynamically adapt to different refresh rate modes (low and high)
Solution Approach 1:
The patent implements dynamic adaptability by introducing a dynamic reference voltage generation mechanism. The reference voltage is no longer fixed but is dynamically adjusted based on the operating mode (low refresh rate or high refresh rate). This is achieved through additional control circuits that sense the operating mode and accordingly adjust the reference voltage applied to the gate control transistor, enabling the same circuit structure to adapt to different refresh rate requirements without requiring separate circuits for each mode.
Solution Approach 2:
The patent changes the voltage parameter of the reference signal to adapt to different operating modes. By varying the reference voltage level based on whether the display operates in low refresh rate mode or high refresh rate mode, the circuit achieves mode-specific optimization. This parameter change allows the gate control transistor to receive appropriate biasing conditions for different refresh rates, improving both adaptability and display quality without fundamentally redesigning the circuit.
2Reliability
If the pixel circuit cannot dynamically control gate voltage, then the circuit design is simple, but the reliability of the display apparatus decreases when switching between modes
Solution Approach 1:
The patent incorporates feedback mechanisms where the operating mode is detected and fed back to the reference voltage generation circuit. This feedback loop ensures that the reference voltage is automatically adjusted according to the current operating mode, maintaining optimal gate control conditions. The feedback mechanism prevents reliability issues by ensuring that the gate voltage remains appropriately biased whether the display is in low or high refresh rate mode, eliminating the need for complex manual intervention or separate control circuits for each mode.
3Productivity
If the pixel circuit uses a single reference voltage level, then the manufacturing process is simple, but the charging efficiency is insufficient for high refresh rate modes
Solution Approach 1:
The patent introduces dynamic reference voltage adjustment that responds to the operating mode. For high refresh rate modes, the system automatically selects a reference voltage level optimized for fast charging and rapid voltage transitions. This dynamic adaptation allows the same manufacturing process to produce a circuit that achieves high charging efficiency in high refresh rate modes without requiring separate manufacturing lines or complex additional components, as the voltage adjustment is achieved through control circuitry rather than hardware redundancy.
Data Source
AI summary
The invention relates to a pixel circuit, a driving method thereof, a display substrate and a display apparatus. The pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a light emitting control sub-circuit and a drive sub-circuit. The first node control sub-circuit is configured to supply a signal of the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal, and supply a signal of the second node to the first node under the control of the third scan signal terminal. The second node control sub-circuit is configured to supply a signal of the reference signal terminal to the second node and a signal of the data signal terminal to the third node under the control of the second reset signal terminal and the first scan signal terminal.