Cascaded Pixel Circuit Sampling for High-SNR Voltage Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Prior art pixel circuits face issues with reduced signal-to-noise ratio (SNR) due to charge redistribution between capacitors and additional errors from offset between read buffers, affecting the accuracy of voltage reading.
Innovation Solution
A pixel circuit design with two sample-and-hold stages connected in cascade, allowing independent reading of voltages from each stage, which cancels out offset errors and maintains high SNR by equalizing signals before sensing, and an adjustable capacitance on the floating diffusion node for different operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If voltages are read out through a single read buffer serially, then device complexity is reduced, but measurement precision deteriorates due to charge redistribution between capacitors
Solution Approach 1:
The patent divides the single read buffer into multiple read buffers (first read buffer and second read buffer) that operate in parallel. Each read buffer independently reads voltages from separate sample-and-hold circuits, eliminating charge redistribution between capacitors and maintaining high signal-to-noise ratio while enabling simultaneous voltage readings.
2Measurement precision
If multiple read buffers are used to read voltages in parallel, then measurement precision is improved, but device complexity increases due to offset errors between buffers
Solution Approach 1:
The patent merges the functionality of multiple read buffers by having them share a common output node. This allows parallel voltage readings to be achieved while reducing device complexity, as the buffers work together rather than independently, eliminating the need for separate output pathways for each buffer.
Solution Approach 2:
The patent introduces an equalization phase before the reading phase where the sample-and-hold circuits are equalized to the same voltage level. This preliminary action ensures that all read buffers start from the same reference point, canceling out offset errors between buffers and improving measurement precision.
3Measurement precision
If sample-and-hold circuits are used to buffer voltages, then measurement precision is improved, but device complexity increases due to charge redistribution
Solution Approach 1:
The patent segments the sample-and-hold functionality into multiple independent circuits (first S/H circuit and second S/H circuit), each with its own holding capacitor. This allows voltages to be buffered independently without charge redistribution between capacitors, maintaining measurement precision while managing device complexity through modular design.
Data Source
AI summary
The present invention provides a pixel circuit. A first S/H stage and the second S/H stage are connected in cascade between a buffer amplifier and an amplifier circuit. During a first and a second time period, a buffered output signal having a first voltage and a second voltage generated by the buffer amplifier are stored serially to the first S/H stage and the second S/H stage. The amplifier circuit senses the first voltage and the second voltage stored in the first S/H stage and the second S/H stage independently for generating a first output signal and a second output signal correspondingly. A calibrated signal is generated according to the first output signal and the second output signal.