Pixel Circuit Layout for Kickback Voltage Uniformity in Displays
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Solution Overview
Problem
Display devices face challenges with high integration and power consumption due to the increasing number of transistors connected to each light emitting element, leading to potential deviations in kickback voltages that cause stains and luminance differences between pixels.
Innovation Solution
The display device incorporates a design with a first active layer, scan line, and compensation control line configurations that form boosting and compensation transistor capacitors, where the planar areas are determined by the width of the second active layer, reducing the deviation of kickback voltages and preventing stains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of transistors connected to each light emitting element is increased to accurately control light emission, then the control precision is improved, but the integration density and power consumption worsen
Solution Approach 1:
The patent merges the boosting capacitor and compensation transistor capacitor into a single overlapping region between the scan line and second active layer, eliminating the need for separate capacitor areas. This combining approach maintains precise control functionality while reducing overall device complexity and improving integration density.
Solution Approach 2:
The patent utilizes vertical stacking and overlapping in the third dimension (z-direction) to create capacitive structures. By forming capacitors through overlapping conductive layers at different heights rather than lateral expansion, the design achieves high precision control without increasing planar footprint, thus resolving the contradiction between control precision and integration density.
2Measurement precision
If the number of transistors connected to each light emitting element is increased to accurately control light emission, then the control precision is improved, but the power consumption worsens
Solution Approach 1:
The patent combines multiple capacitor functions into a single overlapping region, reducing the total number of discrete capacitor structures and associated parasitic elements. This merger reduces overall power consumption while maintaining the precision control functionality provided by the multiple transistor configuration.
Solution Approach 2:
The patent optimizes the capacitance values and geometric parameters of the overlapping regions to achieve the required control precision with minimal energy storage requirements. By carefully tuning capacitor parameters rather than simply increasing transistor count, the design achieves precise control with lower power consumption.
3Stability of the object's composition
If the planar area of capacitors is increased to reduce kickback voltage deviation, then the voltage stability is improved, but the area occupied worsens
Solution Approach 1:
The patent transitions from lateral expansion of capacitor areas to vertical overlapping of conductive layers. By forming capacitors through overlapping layers in the z-direction, the design achieves large effective capacitor area without increasing the planar footprint, thus improving voltage stability while minimizing area occupation.
Solution Approach 2:
The patent nests multiple functional layers within each other in the vertical direction, with the second active layer overlapping both the scan line and compensation control line. This nested arrangement creates multiple capacitive coupling regions that provide voltage stability without requiring additional lateral space.
Data Source
AI summary
A display device is disclosed that may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, extending in a first direction and including a first protruding portion protruding in a second direction crossing the first direction, a first compensation control line disposed on the first active layer, extending in the first direction and spaced apart from the scan line in the second direction, and a second active layer disposed on the scan line and the first compensation control line, overlapping the scan line and the first compensation control line and including a second protruding portion protruding in the first direction. The first protruding portion may be positioned outside the second active layer in the first direction in a plan view.