Pixel Circuit Layout for Longer Leakage Paths in OLED Panels

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Solution Overview

Problem

Existing pixel circuits in display technologies face challenges in maintaining stable potential of light-emitting elements due to short leakage current paths and high leakage currents, which affect the light-emitting efficiency and display quality.

Innovation Solution

The pixel circuit design includes a semiconductor layer forming active layers of transistors with specific gate and source-drain metal layer configurations, where the channel region of the first reset transistor is positioned between the channel regions of the first light emission control and second reset transistors, extending the distance between the second reset transistor and the light-emitting element, thereby increasing the leakage path length and reducing leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the pixel circuit uses conventional transistor layout with short channel paths, then the device complexity is reduced, but the leakage current increases and the light-emitting element potential becomes unstable

Engineering Contradiction:
Improvelight-emitting element potential stabilityVSAvoidtransistor channel arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extends the channel of the reset transistor from a conventional linear path to a two-dimensional path that goes around the light-emitting element. This dimensional change increases the channel length and leakage path without significantly increasing the footprint area, thereby reducing leakage current while maintaining potential stability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The reset transistor channel is segmented into multiple sections that are arranged in a specific pattern around the light-emitting element. This segmentation allows the channel to be distributed in a way that maximizes the leakage path length while maintaining compact overall structure, addressing both reliability and complexity concerns.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If the leakage path length is increased to reduce leakage current, then the light-emitting efficiency is improved, but the transistor area increases

Engineering Contradiction:
Improveleakage currentVSAvoidtransistor area
Core Design Contradiction:
Loss of energyVSArea of stationary object

Solution Approach 1:

By changing the channel arrangement from a linear one-dimensional path to a two-dimensional path that utilizes the space around the light-emitting element, the patent achieves longer leakage paths without proportionally increasing the transistor area. This dimensional optimization allows the channel to efficiently use available space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The reset transistor channel is nested around the light-emitting element, utilizing the space in a concentric or annular pattern. This nesting approach allows the channel to achieve extended length by wrapping around the central element, effectively increasing the leakage path within a compact area.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12046174B2Pixel circuit, display panel, and display device
Publication Date: 2024.07.23 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12046174B2 patent drawing
  • US12046174B2 patent drawing
  • US12046174B2 patent drawing

AI summary

Provided is a pixel circuit. The pixel circuit includes a semiconductor layer disposed on a side of a base substrate, wherein the semiconductor layer is configured to form active layers of transistors in the pixel circuit, the active layer including a channel region, and a source region and a drain region disposed on two sides of the channel region; and a first gate metal layer disposed on the side of the base substrate, wherein the first gate metal layer is configured to form gates of the transistors, the gates of the transistors being arranged in sequence along a first direction, and the gate of each of the transistors being partially overlapped with the channel region.