Display Pixel Circuit With 3D Conductive Line Nesting
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Solution Overview
Problem
Conventional electronic devices with increased signal lines result in larger pixels, reducing display panel resolution and quality.
Innovation Solution
The arrangement of conductive lines on a substrate with specific distance relationships, including transistors with different semiconductor materials, allows for efficient use of space and enhances display panel resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more signal lines are used to drive light-emitting elements, then display brightness and color accuracy are improved, but pixel area increases and resolution decreases
Solution Approach 1:
The patent transitions from planar 2D conductive line arrangement to 3D spatial arrangement by making conductive lines overlap in the vertical dimension. Multiple conductive lines are positioned at different heights (first plane, second plane, third plane) to carry different signals, enabling signal transmission without increasing pixel area while maintaining high display resolution
Solution Approach 2:
The patent implements nesting by placing conductive lines within and across multiple planes, where conductive lines on higher planes are positioned over and near conductive lines on lower planes. This nested arrangement allows multiple signal lines to coexist in a compact vertical space, reducing the horizontal area occupied by signal lines while maintaining signal integrity
2Area of moving object
If conductive lines are arranged closer together to reduce pixel area, then resolution improves, but signal interference between adjacent lines increases
Solution Approach 1:
By moving the solution from 2D to 3D space, the patent allows conductive lines to be physically close in the horizontal plane while being separated vertically across multiple planes. This spatial separation in the vertical dimension effectively reduces electromagnetic interference while maintaining compact pixel area
Solution Approach 2:
The patent introduces insulating layers and dielectric materials between conductive lines on different planes as intermediary elements. These intermediaries provide electrical isolation and prevent signal crosstalk between adjacent conductive lines, enabling closer spacing without increasing interference
3Measurement precision
If conventional planar arrangement of conductive lines is used, then manufacturing is simple, but signal line density is low and resolution is limited
Solution Approach 1:
The patent divides the conductive line structure into multiple discrete planes or layers, with each plane containing specific conductive lines for different signals. This segmentation allows independent fabrication and optimization of each plane, making the complex 3D arrangement more manageable and compatible with existing multi-layer manufacturing processes
Solution Approach 2:
The patent employs universal conductive line structures and materials across different planes that can be fabricated using the same manufacturing processes. By maintaining consistency in material selection and fabrication methods across multiple planes, the patent reduces manufacturing complexity despite the increased structural dimensionality
Data Source
AI summary
An electronic device is provided, including a substrate, an electronic component, and a circuit. The electronic component is disposed on the substrate. The circuit is disposed on the substrate and coupled to the electronic component. The circuit includes a first transistor, a first conductive line, a second transistor, a second conductive line, a third conductive line, and a fourth conductive line. The first transistor includes a first semiconductor and a first gate that overlaps with the first semiconductor. The first conductive line is coupled to the first gate of the first transistor. The second transistor includes a second semiconductor and a second gate that overlaps with the second semiconductor. The second semiconductor is different from the first semiconductor in material. The second conductive line is disposed adjacent to the first conductive line and is coupled to the second gate of the second transistor.