Oxide TFT Pixel Circuit Open Areas for Reliable Display Contacts

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Solution Overview

Problem

Existing display devices face challenges in ensuring reliable electrical connections and uniform ion concentration at the contact areas of oxide semiconductor transistors, which affect the performance and reliability of the display device.

Innovation Solution

The display device incorporates a design with open areas in the gate insulating layer to expose the edges of the source and drain of oxide semiconductor patterns, allowing for uniform ion concentration and improved electrical connections through wider contact holes, using oxide semiconductor patterns and silicon semiconductor transistors in the pixel and gate driving circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate insulating layer is made continuous without open areas, then the insulating performance is improved, but the ion concentration uniformity at contact areas deteriorates

Engineering Contradiction:
Improveinsulating performanceVSAvoidion concentration uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate insulating layer is segmented into a gate insulating film and a separate open area, allowing the insulating layer to be discontinuous at specific contact regions. This segmentation enables ions to reach the semiconductor pattern uniformly at contact areas while maintaining insulating performance in covered regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate insulating layer has different structures at different locations: it is present over the channel portion to maintain insulating performance, and absent at open areas corresponding to contact portions to allow uniform ion concentration. This local differentiation resolves the contradiction between insulating performance and ion concentration uniformity.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If contact holes are made narrower to improve precision, then the manufacturing precision is improved, but the electrical connection reliability deteriorates

Engineering Contradiction:
Improvecontact hole precisionVSAvoidelectrical connection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The contact structure is extended from a single vertical contact hole to a multi-dimensional structure including the open area on the semiconductor pattern surface and the connection electrode extending through multiple insulating layers. This dimensional expansion provides larger contact area and better electrical connection while maintaining precise alignment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The connection electrode acts as an intermediary element that bridges the contact hole and the external circuit. It provides a robust electrical connection path that compensates for the narrow contact hole dimensions, ensuring reliable electrical connection while maintaining manufacturing precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4661625A1Display device and method of manufacturing the same
Publication Date: 2025.12.10 SAMSUNG DISPLAY CO LTD
  • EP4661625A1 patent drawingFigure 1
  • EP4661625A1 patent drawingFigure 2A
  • EP4661625A1 patent drawingFigure 2B

AI summary

A display device (DD) includes a base layer (BL), a pixel circuit (PXC) disposed on the base layer (BL) and comprising a plurality of pixel transistors (T1 to T6, T5a, T6a), a gate insulating layer (GL1, GL2) covering first and second oxide semiconductor patterns (SP1, SP2), and a light emitting element (ED) electrically connected to the pixel circuit (PXC). The plurality of pixel transistors (T1 to T6, T5a, T6a) include a first pixel transistor (T1) including the first oxide semiconductor pattern (SP1) and a second pixel transistor (T2) including the second oxide semiconductor pattern (SP2). An open area (OPA, OPAa) is defined through the gate insulating layer (GL1, GL2) to correspond to a first source (S1) and a first drain (D1) of the first oxide semiconductor pattern (SP1).