Pixel Circuit Layout With Overlapping Scan Line for Higher Display Density
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Solution Overview
Problem
Existing electro-optical devices face challenges in achieving higher density wiring and smaller display sizes due to limitations in control line pitch, which affect display definition and integrity.
Innovation Solution
The electro-optical device incorporates a scanning line and data line with pixel circuits where the scanning line overlaps the gate of the drive transistor, allowing for a narrower pitch and higher density wiring, and includes a scanning line drive circuit that controls the potential changes to prevent fluctuations affecting the drive transistor, ensuring consistent light emission and display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the scanning line is wired not to intersect the gate of the drive transistor, then the layout is simpler and easier to manufacture, but the control line pitch becomes larger which limits display definition and increases device size
Solution Approach 1:
The scanning line is configured to overlap the gate of the drive transistor in the plan view, utilizing the vertical dimension (thickness direction of substrate) to resolve the horizontal spacing constraint. This allows the scanning line to pass through the gate region without electrical interference, effectively reducing the pitch between adjacent scanning lines while maintaining manufacturing feasibility through proper layer stacking.
Solution Approach 2:
The gate insulation layer serves as an intermediary between the scanning line and the gate electrode, providing electrical isolation while allowing the scanning line to be positioned directly over the gate. This mediator enables the scanning line to occupy the same horizontal space as the gate without causing short circuits, thus reducing the control line pitch.
2Area of stationary object
If the scanning line overlaps the gate of the drive transistor, then the control line pitch is reduced enabling higher density wiring and smaller display size, but potential fluctuations from the scanning line may affect the drive transistor operation
Solution Approach 1:
The gate insulation layer acts as an electrical intermediary that isolates the scanning line from the gate electrode, preventing direct electrical interference while allowing the scanning line to overlap the gate for pitch reduction. This insulation layer blocks potential fluctuations from the scanning line from affecting the drive transistor, enabling both compact design and reliable operation.
Solution Approach 2:
The gate insulation layer is applied in advance to prevent harmful electrical coupling between the scanning line and the gate electrode. By establishing this protective barrier before final wiring, the design preemptively counteracts potential interference, allowing the scanning line to be positioned close to the gate without compromising transistor stability.
3Measurement precision
If the pitch between control lines is reduced for higher definition display, then the display definition and pixel density are improved, but the wiring becomes more complex and difficult to manufacture
Solution Approach 1:
The design transitions from a two-dimensional planar layout to a three-dimensional stacked configuration, where the scanning line is positioned in a different vertical layer than the gate electrode. This dimensional change allows adjacent scanning lines to be placed closer together horizontally without increasing wiring complexity, as the overlapping structure is achieved through layer stacking rather than complex routing.
Solution Approach 2:
The gate insulation layer serves multiple functions simultaneously: it provides electrical isolation between the scanning line and gate electrode, enables the scanning line to overlap the gate for pitch reduction, and maintains manufacturing simplicity by using standard insulation techniques. This multi-functional element resolves the contradiction between compact design and ease of manufacture.
Data Source
AI summary
An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines.