Pixel Circuit Parasitic Capacitance Compensation for Display Uniformity

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Solution Overview

Problem

In active matrix organic EL display units, variations in threshold voltage and mobility of drive transistors lead to non-uniform light emission luminance across pixels due to parasitic capacitance, affecting screen uniformity.

Innovation Solution

A display unit with a pixel circuit comprising a first transistor that decreases parasitic capacitance with increased negative gate bias, a second transistor to control current based on sampled voltage, and a retention capacitance to retain sampled voltage, allowing for reduced bootstrap gain variation across pixels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If linear sequential scanning of 1H period is used for writing signal voltage, then writing operation can be performed, but parasitic capacitance of transistor causes bootstrap gain variation and impairs screen uniformity

Engineering Contradiction:
Improvewriting operation speedVSAvoidscreen uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces a bootstrap capacitance connected between the gate and source of the drive transistor to compensate for parasitic capacitance effects. By adding this external capacitance element, the total capacitance at the gate node is increased, which stabilizes the bootstrap gain and reduces pixel-to-pixel variation caused by transistor parasitic capacitance differences.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If drive transistor threshold voltage and mobility are allowed to vary for each pixel, then transistor manufacturing flexibility is maintained, but light emission luminance uniformity is impaired

Engineering Contradiction:
Improvetransistor manufacturing flexibilityVSAvoidlight emission luminance uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The retention capacitance stores the signal voltage written during the scanning period, and the bootstrap capacitance maintains the gate-source voltage relationship. This feedback mechanism ensures that variations in transistor threshold voltage and mobility are compensated, as the stored voltages continue to drive the transistors uniformly across all pixels even when their characteristics differ.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If parasitic capacitance of transistor is present during writing operation, then transistor can function as switch, but bootstrap gain is lowered and varies for each pixel

Engineering Contradiction:
Improvetransistor switching functionVSAvoidbootstrap gain uniformity
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The bootstrap capacitance acts as an intermediary element between the gate and source of the drive transistor. It mediates the voltage relationship by storing the voltage difference and releasing it to maintain proper bootstrap gain, thereby compensating for the detrimental effects of parasitic capacitance while preserving the transistor's switching functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9262963B2Display unit and electronic apparatus
Publication Date: 2016.02.16 MAGNOLIA BLUE CORP
  • US9262963B2 patent drawing
  • US9262963B2 patent drawing
  • US9262963B2 patent drawing

AI summary

A display unit provided with a display panel including a light emitting element and a pixel circuit for each pixel, and a drive circuit configured to drive each of the pixels. The pixel circuit includes: a first transistor configured to sample a voltage corresponding to a picture signal, the first transistor having characteristics that a parasitic capacitance at a time when the first transistor is turned off is decreased as magnitude of negative bias applied to a gate voltage is increased; a second transistor configured to control a current flowing through the light emitting element based on magnitude of the voltage sampled by the first transistor; and a retention capacitance configured to retain the voltage sampled by the first transistor.